| /external/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 148 /// the Op parameter is 'OP', OpRHS is 'C1', and AndRHS is 'C2'. Op is
151 ConstantInt *OpRHS,
157 Together = ConstantExpr::getAnd(AndRHS, OpRHS);
170 if (Together != OpRHS) {
185 return BinaryOperator::CreateOr(And, OpRHS);
202 const APInt& AddRHS = OpRHS->getValue();
229 uint32_t OpRHSVal = OpRHS->getLimitedValue(BitWidth);
249 uint32_t OpRHSVal = OpRHS->getLimitedValue(BitWidth);
269 uint32_t OpRHSVal = OpRHS->getLimitedValue(BitWidth);
276 ShVal = Builder->CreateLShr(ShVal, OpRHS, O
150 OptAndOp(Instruction *Op, ConstantInt *OpRHS, ConstantInt *AndRHS, BinaryOperator &TheAnd) argument
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 192 // the Op parameter is 'OP', OpRHS is 'C1', and AndRHS is 'C2'. Op is
195 ConstantInt *OpRHS,
201 Together = ConstantExpr::getAnd(AndRHS, OpRHS);
214 if (Together != OpRHS) {
229 return BinaryOperator::CreateOr(And, OpRHS);
246 const APInt& AddRHS = cast<ConstantInt>(OpRHS)->getValue();
273 uint32_t OpRHSVal = OpRHS->getLimitedValue(BitWidth);
294 uint32_t OpRHSVal = OpRHS->getLimitedValue(BitWidth);
315 uint32_t OpRHSVal = OpRHS->getLimitedValue(BitWidth);
323 ShVal = Builder->CreateLShr(ShVal, OpRHS, O
194 OptAndOp(Instruction *Op, ConstantInt *OpRHS, ConstantInt *AndRHS, BinaryOperator &TheAnd) argument
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4142 SDValue OpLHS, OpRHS; local
4144 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4178 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
4180 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
4182 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
4186 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
4187 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 5433 SDValue OpLHS, OpRHS; local
5435 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5479 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5484 OpRHS);
5487 OpRHS);
5490 OpRHS);
5493 OpRHS);
5496 OpRHS);
5499 OpRHS);
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 7381 SDValue OpLHS, OpRHS; local
7383 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
7417 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
7419 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
7421 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
7425 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
7426 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 4259 SDValue OpLHS, OpRHS; local
4261 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4287 OpLHS, OpRHS,
4292 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4296 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4300 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6132 SDValue OpLHS, OpRHS; local
6134 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6160 OpLHS, OpRHS,
6165 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
6169 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
6173 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 26757 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1); local
[all...] |