Searched defs:TRC (Results 1 - 16 of 16) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/PTX/
H A DPTXMFInfoExtract.cpp58 const TargetRegisterClass *TRC = MRI.getRegClass(Reg); local
59 MFI->addVirtualRegister(TRC, Reg);
H A DPTXMachineFunctionInfo.h103 void addVirtualRegister(const TargetRegisterClass *TRC, unsigned Reg) { argument
108 UsedRegs[TRC].push_back(Reg);
109 if (TRC == PTX::RegPredRegisterClass)
111 else if (TRC == PTX::RegI16RegisterClass)
113 else if (TRC == PTX::RegI32RegisterClass)
115 else if (TRC == PTX::RegI64RegisterClass)
117 else if (TRC == PTX::RegF32RegisterClass)
119 else if (TRC == PTX::RegF64RegisterClass)
124 name += utostr(UsedRegs[TRC].size() - 1);
142 unsigned getNumRegistersForClass(const TargetRegisterClass *TRC) cons
[all...]
H A DPTXISelLowering.cpp239 TargetRegisterClass* TRC = getRegClassFor(RegVT); local
244 unsigned Reg = MF.getRegInfo().createVirtualRegister(TRC);
300 TargetRegisterClass* TRC = 0; local
304 TRC = PTX::RegPredRegisterClass;
307 TRC = PTX::RegI16RegisterClass;
310 TRC = PTX::RegI32RegisterClass;
313 TRC = PTX::RegI64RegisterClass;
316 TRC = PTX::RegF32RegisterClass;
319 TRC = PTX::RegF64RegisterClass;
325 unsigned Reg = MF.getRegInfo().createVirtualRegister(TRC);
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H A DPTXAsmPrinter.cpp57 const TargetRegisterClass *TRC = MRI.getRegClass(RegNo); local
60 if (PTX::cls ## RegisterClass == TRC) return # clsstr;
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyAsmPrinter.cpp97 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); local
99 if (TRC->hasType(T))
/external/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp430 const TargetRegisterClass &TRC = *getRegClass(Reg); local
431 return TRC.getLaneMask();
H A DRegAllocPBQP.cpp576 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); local
585 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF);
/external/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp77 unsigned Lane, const TargetRegisterClass *TRC);
100 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
136 const TargetRegisterClass *TRC) {
142 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC);
144 return TRC->contains(Reg);
278 const TargetRegisterClass *TRC = local
280 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) {
447 const TargetRegisterClass *TRC) {
448 unsigned Out = MRI->createVirtualRegister(TRC);
135 usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC) argument
444 createExtractSubreg( MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const DebugLoc &DL, unsigned DReg, unsigned Lane, const TargetRegisterClass *TRC) argument
H A DARMISelLowering.cpp7303 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass local
7322 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7327 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
7332 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7349 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7353 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
7358 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7362 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
7367 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
7381 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7407 const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass local
7914 const TargetRegisterClass *TRC = nullptr; local
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/external/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2531 const TargetRegisterClass *TRC; local
2533 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2534 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2537 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
2566 const TargetRegisterClass *TRC; local
2568 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2569 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2570 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2573 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
H A DX86ISelLowering.cpp23959 const TargetRegisterClass *TRC = local
23961 VR = MRI->createVirtualRegister(TRC);
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp1679 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI); local
1680 MRI->constrainRegClass(EvenReg, TRC);
1681 MRI->constrainRegClass(OddReg, TRC);
H A DARMISelLowering.cpp5197 TargetRegisterClass *TRC = local
5199 unsigned scratch = MRI.createVirtualRegister(TRC);
5200 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
5307 TargetRegisterClass *TRC = local
5309 unsigned scratch = MRI.createVirtualRegister(TRC);
5310 unsigned scratch2 = MRI.createVirtualRegister(TRC);
5417 TargetRegisterClass *TRC = local
5419 unsigned storesuccess = MRI.createVirtualRegister(TRC);
5571 const TargetRegisterClass *TRC = local
5592 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5678 const TargetRegisterClass *TRC = local
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/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp2132 TargetRegisterClass *TRC = 0; local
2134 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2135 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2138 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2161 TargetRegisterClass *TRC = 0; local
2163 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2164 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2165 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2168 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
/external/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1685 const TargetRegisterClass *TRC; local
1687 TRC = &Hexagon::PredRegsRegClass;
1689 TRC = &Hexagon::IntRegsRegClass;
1691 TRC = &Hexagon::DoubleRegsRegClass;
1696 unsigned NewReg = MRI.createVirtualRegister(TRC);
/external/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp202 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1); variable
204 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);

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