Searched defs:lane (Results 1 - 23 of 23) sorted by relevance

/external/python/cpython3/Modules/_sha3/kcp/
H A DKeccakP-1600-opt64.c98 UINT64 lane; local
102 lane = data[0];
104 lane = 0;
105 memcpy(&lane, data, length);
107 lane <<= offset*8;
109 UINT64 lane = 0;
112 lane |= ((UINT64)data[i]) << ((i+offset)*8);
114 ((UINT64*)state)[lanePosition] ^= lane;
164 UINT64 lane = (UINT64)curData[0]
172 ((UINT64*)state)[i] ^= lane;
182 UINT64 lane = byte; local
306 UINT64 lane = ((UINT64*)state)[lanePosition]; local
382 UINT64 lane = ((UINT64*)state)[lanePosition]; local
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/external/v8/src/wasm/
H A Dfunction-body-decoder-impl.h299 // Operand for SIMD lane operations.
301 uint8_t lane; member in struct:v8::internal::wasm::SimdLaneOperand
305 lane = decoder->checked_read_u8(pc, 2, "lane");
/external/mesa3d/src/gallium/drivers/swr/rasterizer/core/
H A Dpa_avx.cpp125 for (uint32_t lane = 0; lane < KNOB_SIMD_WIDTH; ++lane)
127 uint32_t input_cp = lane * TotalControlPoints + cp;
132 vec[lane] = pInputVec[input_lane];
432 // Extract vertex 0 to every lane of first vector
630 int lane = pa.numPrims - pa.numPrimsComplete - 1; local
635 targetVtx[lane] = startVtx[0];
H A Dpa.h309 INLINE __m128 swizzleLaneN(const simdvector &a, int lane) argument
311 switch (lane) {
H A Dclip.h369 0 * sizeof(simdvertex), // unused lane
379 // @todo dynamic mask based on actual # of verts generated per lane
395 // tranpose clipper output so that each lane's vertices are in SIMD order
551 // step to the lane
557 // gathers a single component for a given attribute for each SIMD lane
572 DWORD lane; local
573 while (_BitScanForward(&lane, mask))
575 mask &= ~(1 << lane);
576 uint8_t* pBuf = (uint8_t*)pBuffer + pOffsets[lane];
577 *(float*)pBuf = pSrc[lane];
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/external/tensorflow/tensorflow/core/profiler/internal/
H A Dtfprof_timeline.cc241 for (const auto& lane : process.second) {
242 for (const auto& node : lane.second) {
248 process.first, lane.first, "Op",
256 process.first, lane.first, flow_id);
350 const auto& lane = p->lanes[i]; local
352 for (auto cur_it = lane.rbegin(); cur_it != lane.rend(); ++cur_it) {
/external/v8/src/compiler/
H A Dsimd-scalar-lowering.cc403 int32_t lane = OpParameter<int32_t>(node); local
405 GetReplacementsWithType(node->InputAt(0), rep_type)[lane], nullptr,
414 int32_t lane = OpParameter<int32_t>(node); local
415 DCHECK(lane >= 0 && lane <= 3);
418 rep_node[lane] = GetReplacements(repNode)[0];
420 rep_node[lane] = repNode;
H A Dwasm-compiler.cc3620 Node* WasmGraphBuilder::SimdLaneOp(wasm::WasmOpcode opcode, uint8_t lane, argument
3625 return graph()->NewNode(jsgraph()->machine()->Float32x4ExtractLane(lane),
3628 return graph()->NewNode(jsgraph()->machine()->Float32x4ReplaceLane(lane),
3631 return graph()->NewNode(jsgraph()->machine()->Int32x4ExtractLane(lane),
3634 return graph()->NewNode(jsgraph()->machine()->Int32x4ReplaceLane(lane),
3637 return graph()->NewNode(jsgraph()->machine()->Int16x8ExtractLane(lane),
3640 return graph()->NewNode(jsgraph()->machine()->Int16x8ReplaceLane(lane),
3643 return graph()->NewNode(jsgraph()->machine()->Int8x16ExtractLane(lane),
3646 return graph()->NewNode(jsgraph()->machine()->Int8x16ReplaceLane(lane),
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_emit_nv50.cpp125 void emitQUADOP(const Instruction *, uint8_t lane, uint8_t quOp);
834 CodeEmitterNV50::emitQUADOP(const Instruction *i, uint8_t lane, uint8_t quOp) argument
836 code[0] = 0xc0000000 | (lane << 16);
/external/tensorflow/tensorflow/core/kernels/
H A Dreduction_gpu_kernels.cu.h219 const int lane = threadIdx.x % 32; local
228 int col = lane;
244 if (row < num_rows && lane == 0) out[row] = sum;
256 const int lane = threadIdx.x % 32; local
257 const int lane_row = lane / num_cols;
263 int col = lane % num_cols;
285 if (lane < num_cols) sum = op(sum, tmp);
288 if (lane < num_cols) partial_sums[lane * 33 + threadIdx.y] = sum;
/external/vixl/src/aarch64/
H A Dsimulator-aarch64.h307 // unchanged. The lane parameter indicates where in the register the value
311 void Insert(int lane, T new_value) { argument
312 VIXL_ASSERT(lane >= 0);
313 VIXL_ASSERT((sizeof(new_value) + (lane * sizeof(new_value))) <=
315 memcpy(&value_[lane * sizeof(new_value)], &new_value, sizeof(new_value));
325 // Get the lane value as the specified type. The value is truncated if
328 T GetLane(int lane) const {
330 VIXL_ASSERT(lane >= 0);
331 VIXL_ASSERT((sizeof(result) + (lane * sizeof(result))) <= kSizeInBytes);
332 memcpy(&result, &value_[lane * sizeo
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H A Dassembler-aarch64.cc1599 int lane,
1604 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad2);
1632 int lane,
1637 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad3);
1668 int lane,
1673 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad4);
1739 int lane,
1744 LoadStoreStructSingle(vt, lane, dst, NEONLoadStoreSingleStructStore2);
1762 int lane,
1767 LoadStoreStructSingle(vt, lane, ds
1597 ld2(const VRegister& vt, const VRegister& vt2, int lane, const MemOperand& src) argument
1629 ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& src) argument
1664 ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& src) argument
1737 st2(const VRegister& vt, const VRegister& vt2, int lane, const MemOperand& dst) argument
1759 st3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& dst) argument
1783 st4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& dst) argument
1796 LoadStoreStructSingle(const VRegister& vt, uint32_t lane, const MemOperand& addr, NEONLoadStoreSingleStructOp op) argument
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H A Dsimulator-aarch64.cc783 for (int lane = leftmost_lane; lane >= rightmost_lane; lane--) {
785 ? ReadVRegister(code).GetLane<float>(lane)
786 : ReadVRegister(code).GetLane<double>(lane);
899 unsigned lane) {
908 lane);
939 unsigned lane) {
951 PrintVRegisterRawHelper(reg_code, reg_size, lane_size * lane);
953 PrintVRegisterFPHelper(reg_code, lane_size, lane_count, lane);
896 PrintVRead(uintptr_t address, unsigned reg_code, PrintRegisterFormat format, unsigned lane) argument
936 PrintVWrite(uintptr_t address, unsigned reg_code, PrintRegisterFormat format, unsigned lane) argument
4223 int lane = instr->GetNEONLSIndex(index_shift); local
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H A Dmacro-assembler-aarch64.h2574 void Ld1(const VRegister& vt, int lane, const MemOperand& src) { argument
2577 ld1(vt, lane, src);
2591 int lane,
2595 ld2(vt, vt2, lane, src);
2613 int lane,
2617 ld3(vt, vt2, vt3, lane, src);
2640 int lane,
2644 ld4(vt, vt2, vt3, vt4, lane, src);
2743 void St1(const VRegister& vt, int lane, const MemOperand& dst) { argument
2746 st1(vt, lane, ds
2589 Ld2(const VRegister& vt, const VRegister& vt2, int lane, const MemOperand& src) argument
2610 Ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& src) argument
2636 Ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& src) argument
2770 St2(const VRegister& vt, const VRegister& vt2, int lane, const MemOperand& dst) argument
2778 St3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& dst) argument
2787 St4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& dst) argument
[all...]
/external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/
H A Dbuilder_misc.cpp398 /// PRINT("index %d = 0x%p\n",{C(lane), pIndex});
399 /// where C(lane) creates a constant value to print, and pIndex is the Value*
703 /// Byte masks in lower 128 lane of b selects 8 bit values from lower
752 /// @param a - 128bit SIMD lane(16x8bit) of 8bit integer values. Only
769 // Extract 8 values from 128bit lane and sign extend
777 /// @param a - 128bit SIMD lane(8x16bit) of 16bit integer values.
793 // Extract 8 values from 128bit lane and sign extend
802 /// @param a - 256bit SIMD lane(8x32bit) of integer values.
803 /// @param idx - 256bit SIMD lane(8x32bit) of 3 bit lane inde
1233 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local
1322 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local
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H A Dfetch_jit.cpp313 for(uint32_t lane = 0; lane < mVWidth; ++lane)
316 Value* index = VEXTRACT(vCurIndices, C(lane));
331 // We use a full-lane, but don't actually care.
569 // gather SIMD full pixels per lane then shift/mask to move each component to their
618 // store in simd lane
1144 // can fit 2 16 bit integers per vWidth lane
1152 for(int64_t lane = 0; lane < mVWidt
1343 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local
1562 uint32_t lane = ((i == 0) || (i == 2)) ? 0 : 1; local
[all...]
/external/tensorflow/tensorflow/contrib/lite/kernels/internal/optimized/
H A Doptimized_ops.h479 int lane = (in + 8 - input_size) % 4; local
484 buf[lane + 4 * k] += filter_val * input_val;
/external/v8/src/compiler/x64/
H A Dinstruction-selector-x64.cc2284 int32_t lane = OpParameter<int32_t>(node); local
2286 g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));
2291 int32_t lane = OpParameter<int32_t>(node); local
2293 g.UseRegister(node->InputAt(0)), g.UseImmediate(lane),
/external/vixl/src/aarch32/
H A Dassembler-aarch32.cc514 explicit Dt_U_opc1_opc2_1(DataType dt, const DRegisterLane& lane);
517 Dt_U_opc1_opc2_1::Dt_U_opc1_opc2_1(DataType dt, const DRegisterLane& lane) { argument
520 if ((lane.GetLane() & 7) != lane.GetLane()) {
523 SetEncodingValue(0x8 | lane.GetLane());
526 if ((lane.GetLane() & 3) != lane.GetLane()) {
529 SetEncodingValue(0x1 | (lane.GetLane() << 1));
532 if ((lane.GetLane() & 7) != lane
565 Dt_opc1_opc2_1(DataType dt, const DRegisterLane& lane) argument
601 Dt_imm4_1(DataType dt, const DRegisterLane& lane) argument
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H A Ddisasm-aarch32.cc73 DecodeNeon(int lane, SpacingType spacing) argument
74 : lane_(lane), spacing_(spacing), valid_(true) {}
327 DataTypeValue Dt_U_opc1_opc2_1_Decode(uint32_t value, unsigned* lane) { argument
329 *lane = value & 7;
333 *lane = (value >> 1) & 3;
337 *lane = value & 7;
341 *lane = (value >> 1) & 3;
345 *lane = (value >> 2) & 1;
348 *lane = -1;
352 DataTypeValue Dt_opc1_opc2_1_Decode(uint32_t value, unsigned* lane) { argument
369 Dt_imm4_1_Decode(uint32_t value, unsigned* lane) argument
829 int lane = (value >> 1) & 0x7; local
835 int lane = (value >> 2) & 0x3; local
841 int lane = (value >> 3) & 0x1; local
861 int lane = (value >> 1) & 0x7; local
874 int lane = (value >> 2) & 0x3; local
887 int lane = (value >> 3) & 0x1; local
908 int lane = (value >> 1) & 0x7; local
921 int lane = (value >> 2) & 0x3; local
934 int lane = (value >> 3) & 0x1; local
955 int lane = (value >> 1) & 0x7; local
968 int lane = (value >> 2) & 0x3; local
983 int lane = (value >> 3) & 0x1; local
14968 int lane = decode_neon.GetLane(); local
14982 lane), local
15010 int lane = decode_neon.GetLane(); local
15024 lane), local
15054 int lane = decode_neon.GetLane(); local
15069 lane), local
15117 int lane = decode_neon.GetLane(); local
15134 lane), local
15162 int lane = decode_neon.GetLane(); local
15179 lane), local
15209 int lane = decode_neon.GetLane(); local
15227 lane), local
15326 int lane = decode_neon.GetLane(); local
15343 lane), local
15370 int lane = decode_neon.GetLane(); local
15387 lane), local
15416 int lane = decode_neon.GetLane(); local
15435 lane), local
15483 int lane = decode_neon.GetLane(); local
15500 lane), local
15528 int lane = decode_neon.GetLane(); local
15545 lane), local
15575 int lane = decode_neon.GetLane(); local
15593 lane), local
15793 int lane = decode_neon.GetLane(); local
15807 lane), local
15835 int lane = decode_neon.GetLane(); local
15849 lane), local
15879 int lane = decode_neon.GetLane(); local
15894 lane), local
16103 int lane = decode_neon.GetLane(); local
16120 lane), local
16148 int lane = decode_neon.GetLane(); local
16165 lane), local
16195 int lane = decode_neon.GetLane(); local
16213 lane), local
16406 int lane = decode_neon.GetLane(); local
16423 lane), local
16446 int lane = decode_neon.GetLane(); local
16463 lane), local
16488 int lane = decode_neon.GetLane(); local
16507 lane), local
16720 int lane = decode_neon.GetLane(); local
16737 lane), local
16765 int lane = decode_neon.GetLane(); local
16782 lane), local
16812 int lane = decode_neon.GetLane(); local
16830 lane), local
25160 unsigned lane; local
25335 unsigned lane; local
28809 unsigned lane; local
28835 unsigned lane; local
29022 int lane; local
29062 int lane; local
29105 int lane; local
29400 int lane; local
29440 int lane; local
29483 int lane; local
29820 int lane; local
29929 int lane; local
29957 int lane; local
29993 int lane; local
30029 int lane; local
43001 unsigned lane; local
43023 unsigned lane; local
43199 int lane; local
43232 int lane; local
43268 int lane; local
43536 int lane; local
43569 int lane; local
43605 int lane; local
43917 int lane; local
44020 int lane; local
44044 int lane; local
44076 int lane; local
44108 int lane; local
51756 int lane = decode_neon.GetLane(); local
51796 int lane = decode_neon.GetLane(); local
51837 int lane = decode_neon.GetLane(); local
51897 int lane = decode_neon.GetLane(); local
51939 int lane = decode_neon.GetLane(); local
51982 int lane = decode_neon.GetLane(); local
52095 int lane = decode_neon.GetLane(); local
52136 int lane = decode_neon.GetLane(); local
52179 int lane = decode_neon.GetLane(); local
52242 int lane = decode_neon.GetLane(); local
52284 int lane = decode_neon.GetLane(); local
52327 int lane = decode_neon.GetLane(); local
54341 int lane = decode_neon.GetLane(); local
54381 int lane = decode_neon.GetLane(); local
54422 int lane = decode_neon.GetLane(); local
54636 int lane = decode_neon.GetLane(); local
54678 int lane = decode_neon.GetLane(); local
54721 int lane = decode_neon.GetLane(); local
54923 int lane = decode_neon.GetLane(); local
54960 int lane = decode_neon.GetLane(); local
54999 int lane = decode_neon.GetLane(); local
55222 int lane = decode_neon.GetLane(); local
55264 int lane = decode_neon.GetLane(); local
55307 int lane = decode_neon.GetLane(); local
67751 unsigned lane; local
67953 unsigned lane; local
[all...]
/external/valgrind/VEX/priv/
H A Dguest_x86_toIR.c513 least significant lane (rightmost in the register). */
7058 /* Lowest 32-bit lane only SSE binary operation, G = G `op` E. */
7093 /* Lower 64-bit lane only SSE binary operation, G = G `op` E. */
7167 /* Lowest 32-bit lane only unary SSE operation, G = op(E). */
7210 /* Lowest 64-bit lane only unary SSE operation, G = op(E). */
7790 values (aa,bb), computes, for each lane:
7829 value aa, computes, for each lane
8582 assign( argR, getXMMRegLane32F( eregOfRM(modrm), 0/*lowest lane*/ ) );
8593 assign( argL, getXMMRegLane32F( gregOfRM(modrm), 0/*lowest lane*/ ) );
8927 put it into the specified lane o
8932 Int lane; local
11022 Int lane; local
11043 putXMMRegLane16( gregOfRM(modrm), lane & 7, mkexpr(t4) ); local
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H A Dguest_arm64_toIR.c1413 /* Find the offset of the laneNo'th lane of type laneTy in the given
1414 Qreg. Since the host is little-endian, the least significant lane
1420 /* Since the host is little-endian, the least significant lane
1440 /* Put to the least significant lane of a Qreg. */
1455 /* Get from the least significant lane of a Qreg. */
1540 /* Put to a specified lane of a Qreg. */
1557 /* Get from a specified lane of a Qreg. */
3903 // First, interleave at the 64-bit lane size.
3918 // First, interleave at the 32-bit lane size.
3933 // First, interleave at the 16-bit lane siz
9068 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I8); local
9075 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I8); local
9082 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I16); local
9089 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I16); local
9096 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I32); local
9103 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I32); local
9110 IRExpr* lane = getQRegLane(nn, laneNo, Ity_I64); local
[all...]
H A Dguest_amd64_toIR.c1416 least significant lane (rightmost in the register). */
8969 /* Lowest 32-bit lane only SSE binary operation, G = G `op` E. */
9005 /* Lower 64-bit lane only SSE binary operation, G = G `op` E. */
9081 /* Lowest 32-bit lane only unary SSE operation, G = op(E). */
9125 /* Lowest 64-bit lane only unary SSE operation, G = op(E). */
9808 values (aa,bb), computes, for each lane:
9848 value aa, computes, for each lane
10186 0/*lowest lane*/ ) );
10202 0/*lowest lane*/ ) );
10229 0/*lowest lane*/ ) );
14362 Int lane; local
14403 Int lane; local
27896 IRExpr* lane = (laneIs32 ? getYMMRegLane32 : getYMMRegLane64)( rV, i ); local
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