Searched defs:muls (Results 1 - 6 of 6) sorted by relevance
/external/llvm/test/MC/ARM/ |
H A D | mul-v4.s | 6 @ ARMV4: muls r0, r1, r2 @ encoding: [0x91,0x02,0x10,0xe0] 10 muls r0, r1, r2 label
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/external/tensorflow/tensorflow/core/grappler/optimizers/ |
H A D | constant_folding_test.cc | 392 std::vector<Output> muls; local 400 muls.push_back(ops::Mul(s.WithOpName(name), *x, *zeros));
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/external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
H A D | nv50_ir_peephole.cpp | 1304 int muls; local 1308 muls = 1; 1310 muls = 0; 1316 i->setSrc(0, si->getSrc(!muls));
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/external/vixl/src/aarch32/ |
H A D | assembler-aarch32.cc | 7464 void Assembler::muls(Condition cond, Register rd, Register rn, Register rm) { function in class:vixl::aarch32::Assembler 7483 Delegate(kMuls, &Assembler::muls, cond, rd, rn, rm);
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H A D | assembler-aarch32.h | 2650 void muls(Condition cond, Register rd, Register rn, Register rm); 2651 void muls(Register rd, Register rn, Register rm) { muls(al, rd, rn, rm); } function in class:vixl::aarch32::Assembler
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H A D | disasm-aarch32.cc | 1959 void Disassembler::muls(Condition cond, Register rd, Register rn, Register rm) { function in class:vixl::aarch32::Disassembler 7650 muls(Condition::None(), [all...] |
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