Searched defs:src_offset (Results 26 - 50 of 75) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dintel_pixel_bitmap.c110 GLuint src_offset = (x + unpack->SkipPixels) & 0x7; local
118 DBG("%s %d,%d %dx%d bitmap %dx%d skip %d src_offset %d mask %d\n",
119 __func__, x,y,w,h,width,height,unpack->SkipPixels, src_offset, mask);
141 if (test_bit(rowsrc, (col + src_offset) ^ mask)) {
/external/mesa3d/src/mesa/drivers/dri/nouveau/
H A Dnv04_surface.c288 unsigned src_offset = src->offset + sy * src->pitch + sx * src->cpp; local
310 src_offset += src->pitch * count;
/external/mesa3d/src/mesa/drivers/dri/r200/
H A Dr200_blit.c463 * @param[in] src_offset offset of the source image in the @a src_bo
484 intptr_t src_offset,
529 if (src_offset % 32 || dst_offset % 32) {
557 emit_tx_setup(r200, src_mesaformat, dst_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
482 r200_blit(struct gl_context *ctx, struct radeon_bo *src_bo, intptr_t src_offset, mesa_format src_mesaformat, unsigned src_pitch, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, struct radeon_bo *dst_bo, intptr_t dst_offset, mesa_format dst_mesaformat, unsigned dst_pitch, unsigned dst_width, unsigned dst_height, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) argument
H A Dradeon_fbo.c173 uint32_t src_offset = get_depth_z32(rrb, x + pix_x, flipped_y); local
175 untiled_s8z24_map[dst_offset/4] = tiled_s8z24_map[src_offset/4];
213 uint32_t src_offset = get_depth_z16(rrb, x + pix_x, flipped_y); local
215 untiled_z16_map[dst_offset/2] = tiled_z16_map[src_offset/2];
366 uint32_t src_offset = pix_y * rrb->map_pitch + pix_x * rrb->cpp; local
367 tiled_s8z24_map[dst_offset/4] = untiled_s8z24_map[src_offset/4];
399 uint32_t src_offset = pix_y * rrb->map_pitch + pix_x * rrb->cpp; local
400 tiled_z16_map[dst_offset/2] = untiled_z16_map[src_offset/2];
/external/mesa3d/src/mesa/drivers/dri/radeon/
H A Dradeon_blit.c314 * @param[in] src_offset offset of the source image in the @a src_bo
335 intptr_t src_offset,
380 if (src_offset % 32 || dst_offset % 32) {
387 src_width, src_height, src_pitch, src_offset,
408 emit_tx_setup(r100, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
333 r100_blit(struct gl_context *ctx, struct radeon_bo *src_bo, intptr_t src_offset, mesa_format src_mesaformat, unsigned src_pitch, unsigned src_width, unsigned src_height, unsigned src_x_offset, unsigned src_y_offset, struct radeon_bo *dst_bo, intptr_t dst_offset, mesa_format dst_mesaformat, unsigned dst_pitch, unsigned dst_width, unsigned dst_height, unsigned dst_x_offset, unsigned dst_y_offset, unsigned reg_width, unsigned reg_height, unsigned flip_y) argument
H A Dradeon_fbo.c173 uint32_t src_offset = get_depth_z32(rrb, x + pix_x, flipped_y); local
175 untiled_s8z24_map[dst_offset/4] = tiled_s8z24_map[src_offset/4];
213 uint32_t src_offset = get_depth_z16(rrb, x + pix_x, flipped_y); local
215 untiled_z16_map[dst_offset/2] = tiled_z16_map[src_offset/2];
366 uint32_t src_offset = pix_y * rrb->map_pitch + pix_x * rrb->cpp; local
367 tiled_s8z24_map[dst_offset/4] = untiled_s8z24_map[src_offset/4];
399 uint32_t src_offset = pix_y * rrb->map_pitch + pix_x * rrb->cpp; local
400 tiled_z16_map[dst_offset/2] = untiled_z16_map[src_offset/2];
/external/tensorflow/tensorflow/contrib/lite/toco/graph_transformations/
H A Dlstm_utils.cc30 int src_offset = src_start_idx1 * src_stride + src_start_idx2; local
34 int idx_src = src_offset + i * src_stride + j;
/external/v8/src/arm/
H A Ddeoptimizer-arm.cc199 int src_offset = code * kDoubleSize + kNumberOfRegisters * kPointerSize; local
200 __ vldr(d0, sp, src_offset);
272 int src_offset = code * kDoubleSize + double_regs_offset; local
273 __ vldr(reg, r1, src_offset);
/external/v8/src/arm64/
H A Ddeoptimizer-arm64.cc171 int src_offset = kFPRegistersOffset + (i * kDoubleSize); local
172 __ Peek(x2, src_offset);
249 int src_offset = FrameDescription::double_registers_offset() + local
251 __ Ldr(reg, MemOperand(x1, src_offset));
/external/v8/src/mips/
H A Ddeoptimizer-mips.cc201 int src_offset = code * kDoubleSize + kNumberOfRegisters * kPointerSize; local
202 __ ldc1(f0, MemOperand(sp, src_offset));
272 int src_offset = code * kDoubleSize + double_regs_offset; local
273 __ ldc1(fpu_reg, MemOperand(a1, src_offset));
/external/v8/src/mips64/
H A Ddeoptimizer-mips64.cc201 int src_offset = code * kDoubleSize + kNumberOfRegisters * kPointerSize; local
202 __ ldc1(f0, MemOperand(sp, src_offset));
271 int src_offset = code * kDoubleSize + double_regs_offset; local
272 __ ldc1(fpu_reg, MemOperand(a1, src_offset));
/external/v8/src/ppc/
H A Ddeoptimizer-ppc.cc199 int src_offset = code * kDoubleSize + kNumberOfRegisters * kPointerSize; local
200 __ lfd(d0, MemOperand(sp, src_offset));
276 int src_offset = code * kDoubleSize + double_regs_offset; local
277 __ lfd(dreg, MemOperand(r4, src_offset));
/external/v8/src/s390/
H A Ddeoptimizer-s390.cc196 int src_offset = code * kDoubleSize + kNumberOfRegisters * kPointerSize; local
198 __ LoadDouble(d0, MemOperand(sp, src_offset));
274 int src_offset = code * kDoubleSize + double_regs_offset; local
275 __ ld(dreg, MemOperand(r3, src_offset));
/external/v8/src/x64/
H A Ddeoptimizer-x64.cc264 int src_offset = code * kDoubleSize + double_regs_offset; local
265 __ Movsd(xmm_reg, Operand(rbx, src_offset));
/external/libunwind/src/
H A Delfxx.c465 size_t src_offset = 0; local
487 src_remaining = src_size - src_offset;
491 src + src_offset, &src_remaining,
499 src_offset += src_remaining;
/external/mesa3d/src/amd/vulkan/
H A Dradv_meta_buffer.c356 uint64_t src_offset, uint64_t dst_offset,
378 .offset = src_offset,
452 uint64_t src_offset, uint64_t dst_offset,
455 if (size >= 4096 && !(size & 3) && !(src_offset & 3) && !(dst_offset & 3))
457 src_offset, dst_offset, size);
461 src_va += src_offset;
500 uint64_t src_offset = src_buffer->offset + pRegions[r].srcOffset; local
505 src_offset, dest_offset, copy_size);
353 copy_buffer_shader(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_bo *src_bo, struct radeon_winsys_bo *dst_bo, uint64_t src_offset, uint64_t dst_offset, uint64_t size) argument
449 radv_copy_buffer(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_bo *src_bo, struct radeon_winsys_bo *dst_bo, uint64_t src_offset, uint64_t dst_offset, uint64_t size) argument
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_conv.c882 unsigned src_offset = lp_const_offset(src_type); local
889 if (dst_offset > src_offset && src_type.width > dst_type.width && src_shift > 0) {
988 unsigned src_offset = lp_const_offset(src_type); local
1014 if (dst_offset > src_offset) {
/external/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_clear_blit.c313 struct etna_resource_level *src_lev, unsigned int src_offset,
334 srow = smap + src_offset;
420 unsigned src_offset = local
487 reloc.offset = src_offset;
503 .source_offset = src_offset,
531 return etna_manual_blit(dst, dst_lev, dst_offset, src, src_lev, src_offset, blit_info);
311 etna_manual_blit(struct etna_resource *dst, struct etna_resource_level *dst_lev, unsigned int dst_offset, struct etna_resource *src, struct etna_resource_level *src_lev, unsigned int src_offset, const struct pipe_blit_info *blit_info) argument
/external/mesa3d/src/gallium/drivers/nouveau/nv30/
H A Dnv30_transfer.c504 unsigned src_offset = src->offset; local
509 src_offset += (src->y0 * src->pitch) + (src->x0 * src->cpp);
524 PUSH_RELOC(push, src->bo, src_offset, NOUVEAU_BO_LOW, 0, 0);
539 src_offset += src->pitch * lines;
/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_dma.c36 uint64_t src_offset,
51 src_offset += rsrc->gpu_address;
54 if (!(dst_offset % 4) && !(src_offset % 4) && !(size % 4)) {
72 radeon_emit(cs, src_offset);
74 radeon_emit(cs, (src_offset >> 32UL) & 0xff);
76 src_offset += count;
297 uint64_t dst_offset, src_offset; local
303 src_offset= rsrc->surface.level[src_level].offset;
304 src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
305 src_offset
32 si_dma_copy_buffer(struct si_context *ctx, struct pipe_resource *dst, struct pipe_resource *src, uint64_t dst_offset, uint64_t src_offset, uint64_t size) argument
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/external/mesa3d/src/mesa/drivers/dri/i915/
H A Dintel_buffer_objects.c605 GLuint src_offset; local
644 src_bo = intel_bufferobj_source(intel, intel_src, 64, &src_offset);
648 src_bo, read_offset + src_offset, size);
/external/mesa3d/src/mesa/state_tracker/
H A Dst_atom_array.c381 int src_offset, int format,
384 velement->src_offset = src_offset;
394 int src_offset, int format,
408 init_velement(&velements[idx], src_offset,
420 init_velement(&velements[idx], src_offset + 4 * sizeof(float),
426 init_velement(&velements[idx], src_offset, PIPE_FORMAT_R32G32_UINT,
433 init_velement(&velements[idx], src_offset,
499 unsigned src_offset; local
505 src_offset
380 init_velement(struct pipe_vertex_element *velement, int src_offset, int format, int instance_divisor, int vbo_index) argument
391 init_velement_lowered(struct st_context *st, const struct st_vertex_program *vp, struct pipe_vertex_element *velements, int src_offset, int format, int instance_divisor, int vbo_index, int nr_components, GLboolean doubles, GLuint *attr_idx) argument
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/external/pdfium/core/fpdfapi/page/
H A Dcpdf_image.cpp302 int32_t src_offset = 0; local
305 src_offset = row * src_pitch;
308 pDest[dest_offset] = (uint8_t)(src_buf[src_offset + 2] * alpha);
309 pDest[dest_offset + 1] = (uint8_t)(src_buf[src_offset + 1] * alpha);
310 pDest[dest_offset + 2] = (uint8_t)(src_buf[src_offset] * alpha);
312 src_offset += bpp == 24 ? 3 : 4;
/external/v8/src/ia32/
H A Ddeoptimizer-ia32.cc261 int src_offset = code * kDoubleSize; local
262 __ movsd(xmm0, Operand(esp, src_offset));
335 int src_offset = code * kDoubleSize + double_regs_offset; local
336 __ movsd(xmm_reg, Operand(ebx, src_offset));
/external/v8/src/x87/
H A Ddeoptimizer-x87.cc285 int src_offset = code * kDoubleSize; local
286 __ fld_d(Operand(esp, src_offset));

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