Searched refs:op1 (Results 51 - 75 of 167) sorted by relevance

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/external/libvpx/libvpx/vpx_dsp/
H A Dloopfilter.c80 static INLINE void filter4(int8_t mask, uint8_t thresh, uint8_t *op1, argument
84 const int8_t ps1 = (int8_t)*op1 ^ 0x80;
88 const uint8_t hev = hev_mask(thresh, *op1, *op0, *oq0, *oq1);
109 *op1 = signed_char_clamp(ps1 + filter) ^ 0x80;
162 uint8_t *op3, uint8_t *op2, uint8_t *op1,
166 const uint8_t p3 = *op3, p2 = *op2, p1 = *op1, p0 = *op0;
171 *op1 = ROUND_POWER_OF_TWO(p3 + p3 + p2 + 2 * p1 + p0 + q0 + q1, 3);
177 filter4(mask, thresh, op1, op0, oq0, oq1);
235 uint8_t *op2, uint8_t *op1, uint8_t *op0,
241 p2 = *op2, p1 = *op1, p
161 filter8(int8_t mask, uint8_t thresh, uint8_t flat, uint8_t *op3, uint8_t *op2, uint8_t *op1, uint8_t *op0, uint8_t *oq0, uint8_t *oq1, uint8_t *oq2, uint8_t *oq3) argument
232 filter16(int8_t mask, uint8_t thresh, uint8_t flat, uint8_t flat2, uint8_t *op7, uint8_t *op6, uint8_t *op5, uint8_t *op4, uint8_t *op3, uint8_t *op2, uint8_t *op1, uint8_t *op0, uint8_t *oq0, uint8_t *oq1, uint8_t *oq2, uint8_t *oq3, uint8_t *oq4, uint8_t *oq5, uint8_t *oq6, uint8_t *oq7) argument
408 highbd_filter4(int8_t mask, uint8_t thresh, uint16_t *op1, uint16_t *op0, uint16_t *oq0, uint16_t *oq1, int bd) argument
500 highbd_filter8(int8_t mask, uint8_t thresh, uint8_t flat, uint16_t *op3, uint16_t *op2, uint16_t *op1, uint16_t *op0, uint16_t *oq0, uint16_t *oq1, uint16_t *oq2, uint16_t *oq3, int bd) argument
576 highbd_filter16(int8_t mask, uint8_t thresh, uint8_t flat, uint8_t flat2, uint16_t *op7, uint16_t *op6, uint16_t *op5, uint16_t *op4, uint16_t *op3, uint16_t *op2, uint16_t *op1, uint16_t *op0, uint16_t *oq0, uint16_t *oq1, uint16_t *oq2, uint16_t *oq3, uint16_t *oq4, uint16_t *oq5, uint16_t *oq6, uint16_t *oq7, int bd) argument
[all...]
/external/kernel-headers/original/uapi/asm-arm64/asm/
H A Dkvm.h189 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
192 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
/external/libxaac/decoder/
H A Dixheaacd_ps_dec.h134 WORD32 ixheaacd_divide16_pos_dec(WORD32 op1, WORD32 op2);
136 WORD32 ixheaacd_divide16_pos_armv7(WORD32 op1, WORD32 op2);
/external/tensorflow/tensorflow/compiler/xla/service/
H A Dhlo_instruction_test.cc881 HloInstruction* op1 = operand1.get(); local
886 Identical(*HloInstruction::CreateUnary(shape, HloOpcode::kCopy, op1),
887 *HloInstruction::CreateUnary(shape, HloOpcode::kCopy, op1)));
889 Identical(*HloInstruction::CreateUnary(shape, HloOpcode::kCopy, op1),
892 Identical(*HloInstruction::CreateUnary(shape, HloOpcode::kCopy, op1),
893 *HloInstruction::CreateUnary(shape, HloOpcode::kNegate, op1)));
896 EXPECT_TRUE(Identical(*HloInstruction::CreateTuple({op1, op2}),
897 *HloInstruction::CreateTuple({op1, op2})));
898 EXPECT_FALSE(Identical(*HloInstruction::CreateTuple({op1, op2}),
899 *HloInstruction::CreateTuple({op2, op1})));
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/external/v8/src/arm64/
H A Dsimulator-arm64.cc1012 T op1 = reg<T>(instr->Rn());
1013 result = op2 >> lsb | (op1 << ((sizeof(T) * 8) - lsb));
1523 T op1 = reg<T>(instr->Rn());
1531 case AND: result = op1 & op2; break;
1532 case ORR: result = op1 | op2; break;
1533 case EOR: result = op1 ^ op2; break;
1573 T op1 = reg<T>(instr->Rn());
1579 AddWithCarry<T>(true, op1, ~op2, 1);
1582 AddWithCarry<T>(true, op1, op2, 0);
2996 T Simulator::FPAdd(T op1,
[all...]
H A Dsimulator-arm64.h725 T FPAdd(T op1, T op2);
728 T FPDiv(T op1, T op2);
743 T FPMul(T op1, T op2);
746 T FPMulAdd(T a, T op1, T op2);
752 T FPSub(T op1, T op2);
761 T FPProcessNaNs(T op1, T op2);
764 T FPProcessNaNs3(T op1, T op2, T op3);
/external/libvpx/libvpx/vpx_dsp/arm/
H A Dloopfilter_8_neon.asm59 vst1.u8 {d1}, [r3@64], r1 ; store op1
153 ;store op2, op1, op0, oq0
229 ; d1 op1
349 vqadd.s8 d25, d25, d29 ; op1 = clamp(ps1 + filter)
375 vbif d1, d25, d20 ; op1 |= f_op1 & ~(flat & mask)
401 vbit d1, d31, d20 ; op1 |= r_op1 & (flat & mask)
445 vsubw.u8 q14, d3 ; op1 = op2 - p3
446 vsubw.u8 q14, d4 ; op1 -= p2
447 vaddw.u8 q14, d5 ; op1 += p1
448 vaddw.u8 q14, d16 ; op1
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/external/webp/src/dsp/
H A Ddec_neon.c715 uint8x16_t* const op1, uint8x16_t* const op0,
726 *op1 = FlipSignBack_NEON(vqaddq_s8(p1, a3)); // clip(p1 + a3)
734 uint8x16_t* const op1, uint8x16_t* const op0,
758 ApplyFilter4_NEON(p1s, p0s, q0s, q1s, complex_lf_delta, op1, op0, oq0, oq1);
768 uint8x16_t* const op2, uint8x16_t* const op1, uint8x16_t* const op0,
796 *op1 = FlipSignBack_NEON(vqaddq_s8(p1, a2)); // clip(p1 + a2)
805 uint8x16_t* const op2, uint8x16_t* const op1, uint8x16_t* const op0,
831 op2, op1, op0, oq0, oq1, oq2);
845 uint8x16_t op2, op1, op0, oq0, oq1, oq2; local
847 &op2, &op1,
711 ApplyFilter4_NEON( const int8x16_t p1, const int8x16_t p0, const int8x16_t q0, const int8x16_t q1, const int8x16_t delta0, uint8x16_t* const op1, uint8x16_t* const op0, uint8x16_t* const oq0, uint8x16_t* const oq1) argument
730 DoFilter4_NEON( const uint8x16_t p1, const uint8x16_t p0, const uint8x16_t q0, const uint8x16_t q1, const uint8x16_t mask, const uint8x16_t hev_mask, uint8x16_t* const op1, uint8x16_t* const op0, uint8x16_t* const oq0, uint8x16_t* const oq1) argument
764 ApplyFilter6_NEON( const int8x16_t p2, const int8x16_t p1, const int8x16_t p0, const int8x16_t q0, const int8x16_t q1, const int8x16_t q2, const int8x16_t delta, uint8x16_t* const op2, uint8x16_t* const op1, uint8x16_t* const op0, uint8x16_t* const oq0, uint8x16_t* const oq1, uint8x16_t* const oq2) argument
801 DoFilter6_NEON( const uint8x16_t p2, const uint8x16_t p1, const uint8x16_t p0, const uint8x16_t q0, const uint8x16_t q1, const uint8x16_t q2, const uint8x16_t mask, const uint8x16_t hev_mask, uint8x16_t* const op2, uint8x16_t* const op1, uint8x16_t* const op0, uint8x16_t* const oq0, uint8x16_t* const oq1, uint8x16_t* const oq2) argument
862 uint8x16_t op2, op1, op0, oq0, oq1, oq2; local
927 uint8x16_t op2, op1, op0, oq0, oq1, oq2; local
945 uint8x16_t op1, op0, oq0, oq1; local
960 uint8x16_t op2, op1, op0, oq0, oq1, oq2; local
977 uint8x16_t op1, op0, oq0, oq1; local
[all...]
/external/vixl/src/aarch64/
H A Dlogic-aarch64.cc1127 uint16_t Simulator::PolynomialMult(uint8_t op1, uint8_t op2) const { argument
1131 if ((op1 >> i) & 1) {
3572 T Simulator::FPAdd(T op1, T op2) { argument
3573 T result = FPProcessNaNs(op1, op2);
3576 if (std::isinf(op1) && std::isinf(op2) && (op1 != op2)) {
3582 return op1 + op2;
3588 T Simulator::FPSub(T op1, T op2) { argument
3590 VIXL_ASSERT(!std::isnan(op1) && !std::isnan(op2));
3592 if (std::isinf(op1)
3604 FPMul(T op1, T op2) argument
3620 FPMulx(T op1, T op2) argument
3631 FPMulAdd(T a, T op1, T op2) argument
3678 FPDiv(T op1, T op2) argument
3770 FPRecipStepFused(T op1, T op2) argument
3786 FPRSqrtStepFused(T op1, T op2) argument
3984 T op1 = -src1.Float<T>(i); local
4014 T op1 = -src1.Float<T>(i); local
4046 T op1 = src1.Float<T>(i); local
4136 T op1 = src1.Float<T>(i); local
4167 T op1 = -src1.Float<T>(i); local
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/external/crcalc/src/com/hp/creals/
H A DCR.java1062 CR op1; field in class:add_CR
1065 op1 = x;
1072 return scale(op1.get_appr(p-2).add(op2.get_appr(p-2)), -2);
1101 // op1 if selector < 0
1107 CR op1; field in class:select_CR
1112 op1 = x;
1116 if (selector_sign < 0) return op1.get_appr(p);
1118 BigInteger op1_appr = op1.get_appr(p-1);
1125 // op1 and op2 are different; selector != 0;
1139 CR op1; field in class:mult_CR
[all...]
/external/python/cpython2/Lib/
H A Ddecimal.py1173 op1 = _WorkRep(self)
1175 op1, op2 = _normalize(op1, op2, context.prec)
1178 if op1.sign != op2.sign:
1180 if op1.int == op2.int:
1184 if op1.int < op2.int:
1185 op1, op2 = op2, op1
1186 # OK, now abs(op1) > abs(op2)
1187 if op1
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/external/python/cpython3/Lib/
H A D_pydecimal.py1243 op1 = _WorkRep(self)
1245 op1, op2 = _normalize(op1, op2, context.prec)
1248 if op1.sign != op2.sign:
1250 if op1.int == op2.int:
1254 if op1.int < op2.int:
1255 op1, op2 = op2, op1
1256 # OK, now abs(op1) > abs(op2)
1257 if op1
[all...]
/external/libvpx/libvpx/vpx_dsp/mips/
H A Dloopfilter_filters_dspr2.h359 static INLINE void mbfilter_dspr2(uint32_t *op3, uint32_t *op2, uint32_t *op1, argument
363 const uint32_t p3 = *op3, p2 = *op2, p1 = *op1, p0 = *op0;
372 /* *op1 = ROUND_POWER_OF_TWO(p3 + p3 + p2 + p1 + p1 + p0 + q0 + q1, 3) 2 */
425 *op1 = res_op1;
446 /* *op1 = ROUND_POWER_OF_TWO(p3 + p3 + p2 + p1 + p1 + p0 + q0 + q1, 3) 2 */
508 uint32_t *op2, uint32_t *op1, uint32_t *op0, uint32_t *oq0, uint32_t *oq1,
512 const uint32_t p3 = *op3, p2 = *op2, p1 = *op1, p0 = *op0;
606 /* *op1 = ROUND_POWER_OF_TWO(p7 * 2 + p6 + p5 + p4 + p3 + p2 + p1 * 2 +
634 *op1 = res_op1;
506 wide_mbfilter_dspr2( uint32_t *op7, uint32_t *op6, uint32_t *op5, uint32_t *op4, uint32_t *op3, uint32_t *op2, uint32_t *op1, uint32_t *op0, uint32_t *oq0, uint32_t *oq1, uint32_t *oq2, uint32_t *oq3, uint32_t *oq4, uint32_t *oq5, uint32_t *oq6, uint32_t *oq7) argument
/external/mesa3d/src/compiler/glsl/
H A Dir_constant_expression.cpp45 dot_f(ir_constant *op0, ir_constant *op1) argument
47 assert(op0->type->is_float() && op1->type->is_float());
51 result += op0->value.f[c] * op1->value.f[c];
57 dot_d(ir_constant *op0, ir_constant *op1) argument
59 assert(op0->type->is_double() && op1->type->is_double());
63 result += op0->value.d[c] * op1->value.d[c];
H A Dir.cpp194 ir_rvalue *op0, ir_rvalue *op1,
201 this->operands[1] = op1;
357 ir_expression::ir_expression(int op, ir_rvalue *op0, ir_rvalue *op1) argument
362 this->operands[1] = op1;
383 this->type = op1->type;
384 } else if (op1->type->is_scalar()) {
388 this->type = glsl_type::get_mul_type(op0->type, op1->type);
390 assert(op0->type == op1->type);
403 assert(!op1->type->is_matrix());
405 this->type = op1
193 ir_expression(int op, const struct glsl_type *type, ir_rvalue *op0, ir_rvalue *op1, ir_rvalue *op2, ir_rvalue *op3) argument
450 ir_expression(int op, ir_rvalue *op0, ir_rvalue *op1, ir_rvalue *op2) argument
[all...]
H A Dloop_analysis.cpp571 ir_variable *const op1 = rhs->operands[1]->variable_referenced(); local
573 if (((op0 != var) && (op1 != var))
574 || ((op1 == var) && (rhs->operation == ir_binop_sub)))
/external/valgrind/VEX/priv/
H A Dhost_s390_defs.h412 HReg dst; /* op1 */
417 HReg dst_lo; /* also op1 r11 */
427 HReg op1; /* also quotient r11 */ member in struct:__anon28559::__anon28560::__anon28570
454 HReg op1; member in struct:__anon28559::__anon28560::__anon28576
639 s390_insn *s390_insn_divs(UChar size, HReg rem, HReg op1, s390_opnd_RMI op2);
642 s390_insn *s390_insn_cas(UChar size, HReg op1, s390_amode *op2, HReg op3,
661 s390_insn *s390_insn_bfp_compare(UChar size, HReg dst, HReg op1, HReg op2);
685 HReg op1, HReg op2);
H A Dguest_arm64_helpers.c1245 V128 op1; op1.w64[1] = dHi; op1.w64[0] = dLo; local
1249 T.w32[2] = op1.w32[3];
1250 T.w32[1] = op1.w32[2];
1251 T.w32[0] = op1.w32[1];
1256 res->w32[e] = elt + op1.w32[e];
1266 V128 op1; op1.w64[1] = dHi; op1 local
[all...]
/external/lzma/Asm/x86/
H A DXzCrc64Opt.asm111 CRC macro op0:req, op1:req, dest0:req, dest1:req, src:req, t:req
113 op1 dest1, DWORD PTR [r5 + src * 8 + 0800h * t + 4]
/external/tensorflow/tensorflow/python/layers/
H A Dbase_test.py499 layer1, op1 = _gen_layer(op)
500 layer2, op2 = _gen_layer(op1)
505 self.assertEqual(op1.name, 'my_layer_1/my_op:0')
512 layer1, op1 = _gen_layer(op, name='name_1')
513 layer2, op2 = _gen_layer(op1, name='name_2')
518 self.assertEqual(op1.name, 'name_1/my_op:0')
525 layer1, op1 = _gen_layer(op, name='name_2')
526 layer2, op2 = _gen_layer(op1, name='name_3')
531 self.assertEqual(op1.name, 'name_2/my_op:0')
/external/one-true-awk/
H A Dparse.c132 Node *op1(int a, Node *b) function
182 return op1(INDIRECT, celltonode(literal0, CUNK));
/external/valgrind/none/tests/s390x/
H A Ddfp-1.c8 #define DFP_BINOP(insn, op1, op2, type, round, cc) \
10 register type d1 asm("f0") = op1; \
/external/llvm/lib/DebugInfo/DWARF/
H A DDWARFDebugFrame.cpp171 auto op1 = Data.getULEB128(Offset); local
173 addInstruction(Opcode, op1, op2);
181 auto op1 = Data.getULEB128(Offset); local
183 addInstruction(Opcode, op1, op2);
/external/tensorflow/tensorflow/core/kernels/
H A Dslice_op.cc367 T* op1 = op + ((d1 - begin[1]) * out_strides[1]); local
370 memcpy(static_cast<void*>(op1), static_cast<void*>(ip1),
385 T* op1 = op + ((d1 - begin[1]) * out_strides[1]); local
390 T* op2 = op1 + ((d2 - begin[2]) * out_strides[2]);
/external/gemmlowp/meta/generators/
H A Dneon_emitter.py70 def _MakeCompatible(op1, op2, op3):
71 if op1[0] == 'd' or op2[0] == 'd' or op3[0] == 'd':
72 if op1[0] == 'q':
73 op1 = _Low(op1)
78 return (op1, op2, op3)

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