Searched refs:src1 (Results 26 - 50 of 339) sorted by relevance

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/external/webp/src/dsp/
H A Dlossless_enc_msa.c21 #define TRANSFORM_COLOR_8(src0, src1, dst0, dst1, c0, c1, mask0, mask1) do { \
24 VSHF_B2_SH(src0, src0, src1, src1, mask0, mask0, g0, g1); \
28 t1 = __msa_subv_h((v8i16)src1, t1); \
30 t5 = __msa_srli_w((v4i32)src1, 16); \
34 VSHF_B2_UB(src0, t0, src1, t1, mask1, mask1, dst0, dst1); \
63 v16u8 src1, dst1; local
64 LD_UB2(data, 4, src0, src1);
65 TRANSFORM_COLOR_8(src0, src1, dst0, dst1, g2br, r2b, mask0, mask1);
106 v16u8 src1, dst local
[all...]
/external/opencv/cxcore/src/
H A Dcxarithm.cpp60 worktype t0 = __op__((src1)[i], (src2)[i]); \
61 worktype t1 = __op__((src1)[i+1], (src2)[i+1]); \
66 t0 = __op__((src1)[i+2],(src2)[i+2]); \
67 t1 = __op__((src1)[i+3],(src2)[i+3]); \
75 worktype t0 = __op__((src1)[i],(src2)[i]); \
82 ( const type* src1, int step1, const type* src2, int step2, \
84 (src1, step1, src2, step2, dst, step, size) ) \
86 step1/=sizeof(src1[0]); step2/=sizeof(src2[0]); step/=sizeof(dst[0]); \
90 for( ; size.height--; src1 += step1, src2 += step2, dst += step ) \
92 worktype t0 = __op__((src1)[
286 CvMat srcstub1, srcstub2, *src1, *src2; local
761 CvMat srcstub1, *src1 = (CvMat*)srcarr1; local
1321 CvMat srcstub1, *src1 = (CvMat*)srcarr1; local
1669 CvMat srcstub1, *src1 = (CvMat*)srcarr1; local
1869 icvAddWeighted_8u_fast_C1R( const uchar* src1, int step1, double alpha, const uchar* src2, int step2, double beta, double gamma, uchar* dst, int step, CvSize size ) argument
[all...]
/external/clang/test/CodeGenCXX/
H A Ddebug-info-line.cpp84 int *src1();
88 src1())[src2()];
93 int src1[1]; local
97 src1)[src2()];
102 int src1[1][i]; local
106 src1)[src2()];
/external/pcre/dist2/src/sljit/
H A DsljitNativeMIPS_64.c127 FAIL_IF(push_inst(compiler, op_imm | S(src1) | TA(EQUAL_FLAG) | IMM(src2), EQUAL_FLAG)); \
129 FAIL_IF(push_inst(compiler, op_imm | S(src1) | T(dst) | IMM(src2), DR(dst))); \
133 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG)); \
135 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | D(dst), DR(dst))); \
148 FAIL_IF(push_inst(compiler, ins | T(src1) | DA(EQUAL_FLAG) | SH_IMM(src2), EQUAL_FLAG)); \
150 FAIL_IF(push_inst(compiler, ins | T(src1) | D(dst) | SH_IMM(src2), DR(dst))); \
155 FAIL_IF(push_inst(compiler, ins | S(src2) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG)); \
157 FAIL_IF(push_inst(compiler, ins | S(src2) | T(src1) | D(dst), DR(dst))); \
161 sljit_s32 dst, sljit_s32 src1, sljit_sw src2)
168 SLJIT_ASSERT(src1
160 emit_single_op(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 flags, sljit_s32 dst, sljit_s32 src1, sljit_sw src2) argument
[all...]
H A DsljitNativePPC_64.c133 FAIL_IF(push_inst(compiler, EXTSW | S(src1) | A(TMP_REG1))); \
134 src1 = TMP_REG1; \
144 FAIL_IF(push_inst(compiler, EXTSW | S(src1) | A(TMP_REG1))); \
145 src1 = TMP_REG1; \
149 sljit_s32 dst, sljit_s32 src1, sljit_s32 src2)
154 SLJIT_ASSERT(src1 == TMP_REG1);
161 SLJIT_ASSERT(src1 == TMP_REG1);
174 SLJIT_ASSERT(src1 == TMP_REG1);
189 SLJIT_ASSERT(src1 == TMP_REG1);
201 SLJIT_ASSERT(src1
148 emit_single_op(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 flags, sljit_s32 dst, sljit_s32 src1, sljit_s32 src2) argument
[all...]
H A DsljitNativeSPARC_32.c39 sljit_s32 dst, sljit_s32 src1, sljit_sw src2)
48 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
55 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
68 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
78 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
82 SLJIT_ASSERT(src1 == TMP_REG1 && !(flags & SRC2_IMM));
97 return push_inst(compiler, ADD | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst) | (flags & SET_FLAGS));
100 return push_inst(compiler, ADDC | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst) | (flags & SET_FLAGS));
103 return push_inst(compiler, SUB | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst) | (flags & SET_FLAGS));
106 return push_inst(compiler, SUBC | (flags & SET_FLAGS) | D(dst) | S1(src1) | ARG
38 emit_single_op(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 flags, sljit_s32 dst, sljit_s32 src1, sljit_sw src2) argument
[all...]
H A DsljitNativeMIPS_32.c44 FAIL_IF(push_inst(compiler, op_imm | S(src1) | TA(EQUAL_FLAG) | IMM(src2), EQUAL_FLAG)); \
46 FAIL_IF(push_inst(compiler, op_imm | S(src1) | T(dst) | IMM(src2), DR(dst))); \
50 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG)); \
52 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | D(dst), DR(dst))); \
58 FAIL_IF(push_inst(compiler, op_imm | T(src1) | DA(EQUAL_FLAG) | SH_IMM(src2), EQUAL_FLAG)); \
60 FAIL_IF(push_inst(compiler, op_imm | T(src1) | D(dst) | SH_IMM(src2), DR(dst))); \
64 FAIL_IF(push_inst(compiler, op_v | S(src2) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG)); \
66 FAIL_IF(push_inst(compiler, op_v | S(src2) | T(src1) | D(dst), DR(dst))); \
70 sljit_s32 dst, sljit_s32 src1, sljit_sw src2)
77 SLJIT_ASSERT(src1
69 emit_single_op(struct sljit_compiler *compiler, sljit_s32 op, sljit_s32 flags, sljit_s32 dst, sljit_s32 src1, sljit_sw src2) argument
[all...]
/external/libvpx/libvpx/vp8/common/mips/msa/
H A Dsixtap_filter_msa.c35 #define HORIZ_6TAP_FILT(src0, src1, mask0, mask1, mask2, filt_h0, filt_h1, \
41 VSHF_B3_SB(src0, src1, src0, src1, src0, src1, mask0, mask1, mask2, \
52 #define HORIZ_6TAP_4WID_4VECS_FILT(src0, src1, src2, src3, mask0, mask1, \
57 VSHF_B2_SB(src0, src1, src2, src3, mask0, mask0, vec0_m, vec1_m); \
59 VSHF_B2_SB(src0, src1, src2, src3, mask1, mask1, vec2_m, vec3_m); \
61 VSHF_B2_SB(src0, src1, src2, src3, mask2, mask2, vec4_m, vec5_m); \
65 #define HORIZ_6TAP_8WID_4VECS_FILT(src0, src1, src2, src3, mask0, mask1, \
71 VSHF_B2_SB(src0, src0, src1, src
138 v16i8 src0, src1, src2, src3, filt0, filt1, filt2; local
164 v16i8 src0, src1, src2, src3, filt0, filt1, filt2; local
209 v16i8 src0, src1, src2, src3, filt0, filt1, filt2; local
253 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, filt0, filt1, filt2; local
299 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8; local
344 v16i8 src0, src1, src2, src3, src4, src7, src8, src9, src10; local
392 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8; local
458 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8; local
530 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8; local
625 v16i8 src0, src1, src2, src3, filt0, filt1, mask0, mask1; local
650 v16i8 src0, src1, src2, src3, filt0, filt1, mask0, mask1; local
695 v16i8 src0, src1, src2, src3, filt0, filt1, mask0, mask1; local
727 v16i8 src0, src1, src2, src3, src4, src5, src6, src7; local
773 v16i8 src0, src1, src2, src3, src4, src5; local
818 v16i8 src0, src1, src2, src7, src8, src9, src10; local
862 v16i8 src0, src1, src2, src3, src4, src5, src6; local
921 v16i8 src0, src1, src2, src3, src4, src5, src6, filt_hz0, filt_hz1; local
978 v16i8 src0, src1, src2, src3, src4, src5, src6, filt_hz0, filt_hz1; local
1057 v16i8 src0, src1, src2, src3, src4, src5, src6; local
1120 v16i8 src0, src1, src2, src3, src4, src5, src6; local
1205 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8; local
1267 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8; local
[all...]
H A Dbilinear_filter_msa.c33 v16i8 src0, src1, src2, src3, mask; local
42 LD_SB4(src, src_stride, src0, src1, src2, src3);
43 VSHF_B2_UB(src0, src1, src2, src3, mask, mask, vec0, vec1);
54 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, mask; local
63 LD_SB8(src, src_stride, src0, src1, src2, src3, src4, src5, src6, src7);
64 VSHF_B2_UB(src0, src1, src2, src3, mask, mask, vec0, vec1);
90 v16i8 src0, src1, src2, src3, mask; local
98 LD_SB4(src, src_stride, src0, src1, src2, src3);
99 VSHF_B2_UH(src0, src0, src1, src1, mas
112 v16i8 src0, src1, src2, src3, mask, out0, out1; local
184 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, mask; local
247 v16i8 src0, src1, src2, src3, src4; local
271 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8; local
314 v16u8 src0, src1, src2, src3, src4, vec0, vec1, vec2, vec3, filt0; local
336 v16u8 src0, src1, src2, src3, src4, src5, src6, src7, src8; local
388 v16u8 src0, src1, src2, src3, src4; local
435 v16i8 src0, src1, src2, src3, src4, mask; local
464 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, mask; local
520 v16i8 src0, src1, src2, src3, src4, mask, out0, out1; local
561 v16i8 src0, src1, src2, src3, src4, mask, out0, out1; local
650 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, mask; local
[all...]
/external/mesa3d/src/gallium/drivers/freedreno/ir3/
H A Dir3.c205 struct ir3_register *src1 = instr->regs[1]; local
212 if (src1->flags & IR3_REG_RELATIV) {
213 iassert(src1->array.offset < (1 << 10));
214 cat2->rel1.src1 = reg(src1, info, instr->repeat,
217 cat2->rel1.src1_c = !!(src1->flags & IR3_REG_CONST);
219 } else if (src1->flags & IR3_REG_CONST) {
220 iassert(src1->num < (1 << 12));
221 cat2->c1.src1 = reg(src1, inf
285 struct ir3_register *src1 = instr->regs[1]; local
426 struct ir3_register *src1 = instr->regs[1]; local
481 struct ir3_register *dst, *src1, *src2; local
[all...]
/external/libyuv/files/source/
H A Dscale_msa.cc29 v16u8 src0, src1, dst0; local
34 src1 = (v16u8)__msa_ld_b((v16i8*)src_argb, 16);
35 dst0 = (v16u8)__msa_pckod_w((v4i32)src1, (v4i32)src0);
47 v16u8 src0, src1, vec0, vec1, dst0; local
52 src1 = (v16u8)__msa_ld_b((v16i8*)src_argb, 16);
53 vec0 = (v16u8)__msa_pckev_w((v4i32)src1, (v4i32)src0);
54 vec1 = (v16u8)__msa_pckod_w((v4i32)src1, (v4i32)src0);
69 v16u8 src0, src1, src2, src3, vec0, vec1, vec2, vec3, dst0; local
75 src1 = (v16u8)__msa_ld_b((v16i8*)s, 16);
79 vec1 = (v16u8)__msa_vshf_b(shuffler, (v16i8)src1, (v16i
131 v16u8 src0 = {0}, src1 = {0}, src2 = {0}, src3 = {0}; local
182 v16u8 src0, src1, src2, src3, dst0, dst1; local
203 v16u8 src0, src1, src2, src3, vec0, vec1, vec2, vec3, dst0, dst1; local
230 v16u8 src0, src1, src2, src3, src4, src5, src6, src7, dst0, dst1; local
268 v16u8 src0, src1, src2, src3, vec0, vec1, dst0; local
294 v16u8 src0, src1, src2, src3, src4, src5, src6, src7, dst0; local
358 v16u8 src0, src1, vec0; local
387 v16u8 src0, src1, src2, src3, out; local
457 v16u8 src0, src1, src2, src3, src4, src5, out; local
[all...]
H A Drow_msa.cc290 v16u8 src0, src1, src2, src3; local
296 LD_UB4(src, 16, src3, src2, src1, src0);
298 VSHF_B2_UB(src1, src1, src0, src0, shuffler, shuffler, dst1, dst0);
307 v16u8 src0, src1, src2, src3; local
313 LD_UB4(src, 16, src3, src2, src1, src0);
315 VSHF_B2_UB(src1, src1, src0, src0, shuffler, shuffler, dst1, dst0);
377 v16u8 src0, src1, src2; local
389 READYUV422(src_y, src_u, src_v, src0, src1, src
408 v16u8 src0, src1, src2; local
441 v16u8 src0, src1, src2, src3; local
477 v16u8 src0, src1, src2, src3, src4, dst0, dst1, dst2; local
530 v16u8 src0, src1, src2, dst0; local
568 v16u8 src0, src1, src2, dst0; local
608 v16u8 src0, src1, src2, dst0; local
643 v16u8 src0, src1, src2, src3, dst0, dst1; local
662 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
690 v16u8 src0, src1, src2, src3, dst0, dst1; local
708 v16u8 src0, src1, src2, src3, dst0, dst1; local
727 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
755 v16u8 src0, src1, src2, src3, dst0, dst1; local
773 v16u8 src0, src1, src2, src3, vec0, vec1, vec2, vec3, dst0; local
824 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
937 v16u8 src0, src1, src2, src3, dst0, dst1, dst2; local
961 v16u8 src0, src1, src2, src3, dst0, dst1, dst2; local
985 v16u8 src0, src1, dst0; local
1019 v16u8 src0, src1, dst0; local
1059 v16u8 src0, src1; local
1085 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; local
1157 v16u8 src0, src1, dst0; local
1196 v16u8 src0, src1, src2, src3, dst0, dst1; local
1217 v16u8 src0, src1, src2, src3, dst0, dst1; local
1235 v16u8 src0, src1, dst0, dst1; local
1303 v16u8 src0, src1, dst0, vec0, vec1; local
1347 v16u8 src0, src1, dst0, dst1; local
1407 v16u8 src0, src1, vec0, vec1, dst0, dst1; local
1432 v16u8 src0, src1, dst0, dst1, vec0, vec1, vec2, vec3, vec4, vec5; local
1475 v16u8 src0, src1; local
1504 v8u16 src0, src1; local
1552 v8u16 src0, src1, vec0, vec1, vec2, vec3, vec4, vec5; local
1597 v16u8 src0, src1, src2; local
1622 v16u8 src0, src1, src2; local
1647 v8u16 src0, src1, vec0, vec1, vec2, vec3, vec4, vec5; local
1704 v8u16 src0, src1, vec0, vec1, vec2, vec3, vec4, vec5, vec6, vec7; local
1767 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local
1808 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local
1856 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local
1937 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local
2017 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
2123 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
2225 v16u8 src0, src1, res0, res1, dst0, dst1; local
2262 v16u8 src0, src1, dst0; local
2298 v16u8 src0, src1, res0, res1, dst0, dst1; local
2335 v16u8 src0, src1, vec0, dst0, dst1, dst2, dst3; local
2363 v16u8 src0, src1, src2, src3, dst0, dst1; local
2384 v16u8 src0, src1, vec0, vec1, vec2; local
2409 v16u8 src0, src1, src2, src3, dst0; local
2429 v16u8 src0, src1, src2, src3, dst0; local
2449 v16u8 src0, src1, src2, src3, dst0; local
2469 v16u8 src0, src1, src2, src3, dst0; local
2495 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
2598 v16u8 src0, src1, src2, src3; local
2664 v16u8 src0, src1, src2, dst0, dst1; local
2803 v16u8 src0, src1, src2; local
2831 v16u8 src0, src1, src2; local
2865 v16u8 src0, src1, src2, src3, dst0, dst1; local
2930 v16u8 src0, src1, src2, src3, src4, dst0, dst1, dst2; local
2958 v16u8 src0, src1, dst0, dst1; local
[all...]
/external/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_exec.c132 const union tgsi_exec_channel *src1,
135 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
136 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
137 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
138 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
144 const union tgsi_exec_channel *src1,
130 micro_clamp(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) argument
142 micro_cmp(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) argument
373 micro_dldexp(union tgsi_double_channel *dst, const union tgsi_double_channel *src0, union tgsi_exec_channel *src1) argument
506 micro_lrp(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) argument
518 micro_mad(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) argument
592 micro_seq(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
603 micro_sge(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
634 micro_sgt(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
655 micro_sle(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
666 micro_slt(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
677 micro_sne(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
898 micro_u64shl(union tgsi_double_channel *dst, const union tgsi_double_channel *src0, union tgsi_exec_channel *src1) argument
914 micro_i64shr(union tgsi_double_channel *dst, const union tgsi_double_channel *src0, union tgsi_exec_channel *src1) argument
930 micro_u64shr(union tgsi_double_channel *dst, const union tgsi_double_channel *src0, union tgsi_exec_channel *src1) argument
1362 micro_add(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
1393 micro_lt( union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2, const union tgsi_exec_channel *src3 ) argument
1407 micro_max(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
1418 micro_min(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
1429 micro_mul(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
1470 micro_sub(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
3817 union tgsi_exec_channel src1; local
3865 union tgsi_exec_channel src1; local
4634 micro_shl(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4650 micro_and(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4661 micro_or(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4672 micro_xor(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4683 micro_mod(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4704 micro_fseq(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4715 micro_fsge(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4726 micro_fslt(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4737 micro_fsne(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4748 micro_idiv(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4759 micro_imax(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4770 micro_imin(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4781 micro_isge(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4792 micro_ishr(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4808 micro_islt(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4839 micro_uadd(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4850 micro_udiv(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4861 micro_umad(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) argument
4873 micro_umax(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4884 micro_umin(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4895 micro_umod(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4906 micro_umul(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4917 micro_imul_hi(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4930 micro_umul_hi(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4943 micro_useq(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4954 micro_usge(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4965 micro_ushr(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4981 micro_uslt(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
4992 micro_usne(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1) argument
5013 micro_ucmp(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) argument
5028 micro_ibfe(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) argument
5050 micro_ubfe(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2) argument
5072 micro_bfi(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src0, const union tgsi_exec_channel *src1, const union tgsi_exec_channel *src2, const union tgsi_exec_channel *src3) argument
[all...]
/external/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_test_blend.c48 typedef void (*blend_test_ptr_t)(const void *src, const void *src1,
155 LLVMValueRef src1; local
176 src1 = LLVMBuildLoad(builder, src1_ptr, "src1");
181 src1, NULL, dst, NULL, con, NULL, swizzle, 4);
200 const double *src1,
250 term[0] = factor[0] * src1[0]; /* R */
251 term[1] = factor[1] * src1[1]; /* G */
252 term[2] = factor[2] * src1[2]; /* B */
255 term[0] = factor[0] * src1[
196 compute_blend_ref_term(unsigned rgb_factor, unsigned alpha_factor, const double *factor, const double *src, const double *src1, const double *dst, const double *con, double *term) argument
360 compute_blend_ref(const struct pipe_blend_state *blend, const double *src, const double *src1, const double *dst, const double *con, double *res) argument
468 uint8_t *src, *src1, *dst, *con, *res, *ref; local
[all...]
/external/opencv/cv/src/
H A Dcvderiv.cpp575 const int *src0 = src[-1], *src1 = src[0], *src2 = src[1]; local
580 int s0 = src0[i] - src1[i]*2 + src2[i] + src1[i+width];
581 int s1 = src0[i+1] - src1[i+1]*2 + src2[i+1] + src1[i+width+1];
586 dst[i] = (short)(src0[i] - src1[i]*2 + src2[i] + src1[i+width]);
591 int s0 = src0[i] - src1[i]*2 + src2[i] +
592 src0[i+width] + src1[i+width]*2 + src2[i+width];
593 int s1 = src0[i+1] - src1[
609 const int *src0 = src[-2], *src1 = src[-1], *src2 = src[0], *src3 = src[1], *src4 = src[2]; local
643 const int* src1 = src[k] + i, *src2 = src[-k] + i; local
659 const int* src1 = src[k] + i, *src2 = src[-k] + i; local
675 const int* src1 = src[k] + i, *src2 = src[-k] + i; local
717 const float *src0 = src[-1], *src1 = src[0], *src2 = src[1]; local
751 const float *src0 = src[-2], *src1 = src[-1], *src2 = src[0], *src3 = src[1], *src4 = src[2]; local
772 const float* src1 = src[k] + i, *src2 = src[-k] + i; local
788 const float* src1 = src[k] + i, *src2 = src[-k] + i; local
[all...]
/external/swiftshader/src/Shader/
H A DPixelPipeline.hpp75 void ADD(Vector4s &dst, Vector4s &src0, Vector4s &src1);
76 void SUB(Vector4s &dst, Vector4s &src0, Vector4s &src1);
77 void MAD(Vector4s &dst, Vector4s &src0, Vector4s &src1, Vector4s &src2);
78 void MUL(Vector4s &dst, Vector4s &src0, Vector4s &src1);
79 void DP3(Vector4s &dst, Vector4s &src0, Vector4s &src1);
80 void DP4(Vector4s &dst, Vector4s &src0, Vector4s &src1);
81 void LRP(Vector4s &dst, Vector4s &src0, Vector4s &src1, Vector4s &src2);
100 void TEXM3X3SPEC(Vector4s &dst, Float4 &u, Float4 &v, Float4 &s, int stage, Vector4s &src0, Vector4s &src1);
104 void CND(Vector4s &dst, Vector4s &src0, Vector4s &src1, Vector4s &src2);
105 void CMP(Vector4s &dst, Vector4s &src0, Vector4s &src1, Vector4
[all...]
/external/libvpx/libvpx/vpx_dsp/mips/
H A Dvpx_convolve8_vert_msa.c19 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; local
31 LD_SB7(src, src_stride, src0, src1, src2, src3, src4, src5, src6);
34 ILVR_B4_SB(src1, src0, src3, src2, src5, src4, src2, src1, src10_r, src32_r,
70 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; local
81 LD_SB7(src, src_stride, src0, src1, src2, src3, src4, src5, src6);
82 XORI_B7_128_SB(src0, src1, src2, src3, src4, src5, src6);
84 ILVR_B4_SB(src1, src0, src3, src2, src5, src4, src2, src1, src10_r, src32_r,
124 v16i8 src0, src1, src local
205 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; local
303 v16i8 src0, src1, src2, src3, src4; local
327 v16i8 src0, src1, src2, src3, src4, src5, src6, src7, src8; local
370 v16u8 src0, src1, src2, src3, src4, vec0, vec1, vec2, vec3, filt0; local
393 v16u8 src0, src1, src2, src3, src4, src5, src6, src7, src8; local
446 v16u8 src0, src1, src2, src3, src4; local
494 v16u8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9; local
562 v16u8 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; local
[all...]
H A Dsub_pixel_variance_msa.c45 uint32_t src0, src1, src2, src3; local
55 LW4(src_ptr, src_stride, src0, src1, src2, src3);
60 INSERT_W4_UB(src0, src1, src2, src3, src);
80 v16u8 src0, src1, src2, src3; local
89 LD_UB4(src_ptr, src_stride, src0, src1, src2, src3);
94 PCKEV_D4_UB(src1, src0, src3, src2, ref1, ref0, ref3, ref2, src0, src1,
96 AVER_UB2_UB(src0, pred0, src1, pred1, src0, src1);
98 CALC_MSE_AVG_B(src1, ref
169 v16u8 src0, src1, ref0, ref1, pred0, pred1; local
227 v16u8 src0, src1, ref0, ref1, pred0, pred1; local
287 v16u8 src0, src1, src2, src3; local
336 v16u8 src0, src1, src2, src3; local
389 v16i8 src0, src1, src2, src3; local
428 v16i8 src0, src1, src2, src3; local
468 v16i8 src0, src1, src2, src3, src4, src5, src6, src7; local
552 v16u8 src0, src1, src2, src3, src4, out; local
595 v16u8 src0, src1, src2, src3, src4; local
639 v16u8 src0, src1, src2, src3, src4; local
735 v16u8 src0, src1, src2, src3, src4; local
784 v16u8 src0, src1, src2, src3, src4; local
840 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
955 v16i8 src0, src1, src2, src3; local
1000 v16i8 src0, src1, src2, src3; local
1048 v16i8 src0, src1, src2, src3, src4, src5, src6, src7; local
1154 v16u8 src0, src1, src2, src3, src4; local
1201 v16u8 src0, src1, src2, src3, src4; local
1250 v16u8 src0, src1, src2, src3, src4; local
1365 v16u8 src0, src1, src2, src3, src4; local
1416 v16u8 src0, src1, src2, src3, src4; local
1480 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
[all...]
H A Davg_msa.c17 v16u8 src0, src1, src2, src3, src4, src5, src6, src7; local
21 LD_UB8(src, src_stride, src0, src1, src2, src3, src4, src5, src6, src7);
22 HADD_UB4_UH(src0, src1, src2, src3, sum0, sum1, sum2, sum3);
39 uint32_t src0, src1, src2, src3; local
45 LW4(src, src_stride, src0, src1, src2, src3);
46 INSERT_W4_UB(src0, src1, src2, src3, vec);
61 v8i16 src0, src1, src2, src3, src4, src5, src6, src7; local
64 LD_SH8(src, src_stride, src0, src1, src2, src3, src4, src5, src6, src7);
65 BUTTERFLY_8(src0, src2, src4, src6, src7, src5, src3, src1, tmp0, tmp2, tmp4,
67 BUTTERFLY_8(tmp0, tmp1, tmp4, tmp5, tmp7, tmp6, tmp3, tmp2, src0, src1, src
86 v8i16 src0, src1, src2, src3, src4, src5, src6, src7, src8, src9, src10; local
259 v8i16 src0, src1, src2, src3, src4, src5, src6, src7; local
569 v8i16 src0, src1, src2, src3, src4, src5, src6, src7, ref0, ref1, ref2; local
[all...]
/external/v8/src/arm/
H A Dsimulator-arm.cc4011 T src1[kLanes], src2[kLanes]; local
4012 simulator->get_q_register(Vn, src1);
4015 src1[i] = Clamp<T>(Widen(src1[i]) + Widen(src2[i]));
4017 simulator->set_q_register(Vd, src1);
4023 T src1[kLanes], src2[kLanes]; local
4024 simulator->get_q_register(Vn, src1);
4027 src1[i] = Clamp<T>(Widen(src1[i]) - Widen(src2[i]));
4029 simulator->set_q_register(Vd, src1);
4074 uint32_t src1[4]; local
4087 uint32_t src1[4], src2[4]; local
4128 int8_t src1[16], src2[16]; local
4141 int16_t src1[8], src2[8]; local
4154 int32_t src1[4], src2[4]; local
4178 int8_t src1[16], src2[16]; local
4191 int16_t src1[8], src2[8]; local
4204 int32_t src1[4], src2[4]; local
4229 uint8_t src1[16], src2[16]; local
4239 uint16_t src1[8], src2[8]; local
4249 uint32_t src1[4], src2[4]; local
4266 uint8_t src1[16], src2[16]; local
4276 uint16_t src1[8], src2[8]; local
4286 uint32_t src1[4], src2[4]; local
4308 uint8_t src1[16], src2[16]; local
4318 uint16_t src1[8], src2[8]; local
4328 uint32_t src1[4], src2[4]; local
4348 float src1[4], src2[4]; local
4369 float src1[4], src2[4]; local
4384 float src1[4], src2[4]; local
4450 uint8_t src1[16], src2[16], dst[16]; local
4582 uint32_t dst[4], src1[4], src2[4]; local
4593 uint64_t src1, src2; local
4601 uint32_t src1[4], src2[4]; local
4641 uint8_t src1[16], src2[16]; local
4654 uint16_t src1[8], src2[8]; local
4667 uint32_t src1[4], src2[4]; local
4691 uint8_t src1[16], src2[16]; local
4704 uint16_t src1[8], src2[8]; local
4717 uint32_t src1[4], src2[4]; local
4741 uint8_t src1[16], src2[16]; local
4751 uint16_t src1[8], src2[8]; local
4761 uint32_t src1[4], src2[4]; local
4779 uint8_t src1[16], src2[16]; local
4789 uint16_t src1[8], src2[8]; local
4799 uint32_t src1[4], src2[4]; local
4818 float src1[4], src2[4]; local
4834 float src1[4], src2[4]; local
4979 uint8_t src1[16], src2[16], dst1[16], dst2[16]; local
4993 uint16_t src1[8], src2[8], dst1[8], dst2[8]; local
5007 uint32_t src1[4], src2[4], dst1[4], dst2[4]; local
[all...]
H A Dassembler-arm.h808 void and_(Register dst, Register src1, const Operand& src2,
811 void eor(Register dst, Register src1, const Operand& src2,
814 void sub(Register dst, Register src1, const Operand& src2,
816 void sub(Register dst, Register src1, Register src2,
818 sub(dst, src1, Operand(src2), s, cond);
821 void rsb(Register dst, Register src1, const Operand& src2,
824 void add(Register dst, Register src1, const Operand& src2,
826 void add(Register dst, Register src1, Register src2,
828 add(dst, src1, Operand(src2), s, cond);
831 void adc(Register dst, Register src1, cons
[all...]
/external/mesa3d/src/gallium/drivers/swr/rasterizer/core/
H A Dblend.h32 void GenerateBlendFactor(SWR_BLEND_FACTOR func, simdvector &constantColor, simdvector &src, simdvector &src1, simdvector &dst, simdvector &out) argument
143 result.x = src1.x;
144 result.y = src1.y;
145 result.z = src1.z;
146 result.w = src1.w;
150 result.x = result.y = result.z = result.w = src1.w;
154 result.x = _simd_sub_ps(_simd_set1_ps(1.0f), src1.x);
155 result.y = _simd_sub_ps(_simd_set1_ps(1.0f), src1.y);
156 result.z = _simd_sub_ps(_simd_set1_ps(1.0f), src1.z);
157 result.w = _simd_sub_ps(_simd_set1_ps(1.0f), src1
281 Blend(const SWR_BLEND_STATE *pBlendState, const SWR_RENDER_TARGET_BLEND_STATE *pState, simdvector &src, simdvector& src1, BYTE *pDst, simdvector &result) argument
[all...]
/external/vixl/src/aarch64/
H A Dlogic-aarch64.cc712 const LogicVRegister& src1,
717 int64_t sa = src1.Int(vform, i);
719 uint64_t ua = src1.Uint(vform, i);
756 const LogicVRegister& src1,
761 return cmp(vform, dst, src1, imm_reg, cond);
767 const LogicVRegister& src1,
771 uint64_t ua = src1.Uint(vform, i);
781 const LogicVRegister& src1,
787 uint64_t ua = src1.UintLeftJustified(vform, i);
812 const LogicVRegister& src1,
710 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument
754 cmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, int imm, Condition cond) argument
765 cmptst(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
779 add(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
810 addp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
822 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
833 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
844 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
856 mul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
867 mla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
878 mls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
889 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
901 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
913 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
925 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
937 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
949 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
961 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
973 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
985 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
997 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1009 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1021 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1033 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1045 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1057 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1069 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1081 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1093 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1105 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1116 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
1139 pmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1153 pmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1169 pmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1186 sub(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1217 and_(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1229 orr(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1241 orn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1253 eor(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1265 bic(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1294 bif(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1310 bit(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1326 bsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1342 sminmax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument
1363 smax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1371 smin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1379 sminmaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument
1407 smaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1415 sminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1522 uminmax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument
1543 umax(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1551 umin(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1559 uminmaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool max) argument
1587 umaxp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1595 uminp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1910 sshl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
1970 ushl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2217 absdiff(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool issigned) argument
2238 saba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2250 uaba(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2401 ext(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
2843 uaddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2855 uaddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2867 uaddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2878 uaddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2889 saddl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2901 saddl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2913 saddw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2924 saddw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2935 usubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2947 usubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2959 usubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2970 usubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2981 ssubl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
2993 ssubl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3005 ssubw(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3016 ssubw2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3027 uabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3039 uabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3051 sabal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3063 sabal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3075 uabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3087 uabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3099 sabdl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3111 sabdl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3123 umull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3135 umull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3147 smull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3159 smull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3171 umlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3183 umlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3195 smlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3207 smlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3219 umlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3231 umlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3243 smlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3255 smlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3267 sqdmlal(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3277 sqdmlal2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3287 sqdmlsl(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3297 sqdmlsl2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3307 sqdmull(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3317 sqdmull2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3327 sqrdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, bool round) argument
3357 sqdmulh(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3365 addhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3370 add(VectorFormatDoubleWidth(vform), temp, src1, src2); local
3376 addhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3387 raddhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3392 add(VectorFormatDoubleWidth(vform), temp, src1, src2); local
3398 raddhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3409 subhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3414 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); local
3420 subhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3431 rsubhn(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3436 sub(VectorFormatDoubleWidth(vform), temp, src1, src2); local
3442 rsubhn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3453 trn1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3473 trn2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3493 zip1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3513 zip2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3533 uzp1(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3552 uzp2(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3967 fnmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3978 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
3993 frecps(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4008 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4023 frsqrts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4038 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument
4077 fcmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument
4109 fabscmp(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, Condition cond) argument
4130 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4146 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4161 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4177 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4247 fabd(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2) argument
4351 fmul(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
4371 fmla(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
4391 fmls(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
4411 fmulx(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src1, const LogicVRegister& src2, int index) argument
[all...]
/external/libmpeg2/common/x86/
H A Dimpeg2_inter_pred_sse42_intr.c225 UWORD8 *src1, *src2; local
233 src1 = buf_src1->pu1_y;
237 src1_r0 = _mm_loadu_si128((__m128i *) (src1));
238 src1_r1 = _mm_loadu_si128((__m128i *) (src1 + 16));
239 src1_r2 = _mm_loadu_si128((__m128i *) (src1 + 2 * 16));
240 src1_r3 = _mm_loadu_si128((__m128i *) (src1 + 3 * 16));
258 src1 += 4 * 16;
261 src1_r0 = _mm_loadu_si128((__m128i *) (src1));
262 src1_r1 = _mm_loadu_si128((__m128i *) (src1 + 16));
263 src1_r2 = _mm_loadu_si128((__m128i *) (src1
[all...]
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_vec4_builder.h270 const src_reg &src1) const
279 fix_math_operand(src1))));
282 return emit(instruction(opcode, dst, src0, src1));
291 const src_reg &src1, const src_reg &src2) const
300 fix_3src_operand(src1),
304 return emit(instruction(opcode, dst, src0, src1, src2));
331 * conditional mod evaluates to true, otherwise select \p src1.
337 const src_reg &src1, brw_conditional_mod mod) const
342 fix_unsigned_negate(src1)));
375 op(const dst_reg &dst, const src_reg &src0, const src_reg &src1) cons
290 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1, const src_reg &src2) const argument
336 emit_minmax(const dst_reg &dst, const src_reg &src0, const src_reg &src1, brw_conditional_mod mod) const argument
453 CMP(const dst_reg &dst, const src_reg &src0, const src_reg &src1, brw_conditional_mod condition) const argument
487 IF(const src_reg &src0, const src_reg &src1, brw_conditional_mod condition) const argument
[all...]

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