/external/v8/src/x64/ |
H A D | assembler-x64.cc | 3958 XMMRegister src2) { 3961 emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW1); 3963 emit_sse_operand(dst, src2); 3968 const Operand& src2) { 3971 emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW1); 3973 emit_sse_operand(dst, src2); 3978 XMMRegister src2) { 3981 emit_vex_prefix(dst, src1, src2, kLIG, k66, k0F38, kW0); 3983 emit_sse_operand(dst, src2); 3988 const Operand& src2) { 3957 vfmasd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument 3967 vfmasd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument 3977 vfmass(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument 3987 vfmass(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument 4054 vinstr(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2, SIMDPrefix pp, LeadingOpcode m, VexW w) argument 4064 vinstr(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2, SIMDPrefix pp, LeadingOpcode m, VexW w) argument 4075 vps(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument 4085 vps(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument 4095 vpd(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument 4105 vpd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument 4133 vss(byte op, XMMRegister dst, XMMRegister src1, XMMRegister src2) argument 4143 vss(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2) argument [all...] |
/external/mesa3d/src/gallium/drivers/ilo/shader/ |
H A D | toy_compiler_disasm.c | 108 struct disasm_src_operand src2; member in union:disasm_inst::__anon16242 548 inst->u.src2.base.type = inst->src0.base.type; 556 inst->u.src2.base.type = GEN6_TYPE_F; 573 inst->u.src2.base.file = GEN6_FILE_GRF; 574 inst->u.src2.negate = (bool) (dw1 & GEN6_3SRC_SRC2_NEGATE); 575 inst->u.src2.absolute = (bool) (dw1 & GEN6_3SRC_SRC2_ABSOLUTE); 602 inst->u.src2.negate = (bool) (dw1 & GEN8_3SRC_SRC2_NEGATE); 603 inst->u.src2.absolute = (bool) (dw1 & GEN8_3SRC_SRC2_ABSOLUTE); 612 inst->u.src2.base.file = GEN6_FILE_GRF; 613 inst->u.src2 [all...] |
/external/skia/gm/ |
H A D | image.cpp | 68 SkRect src1, src2, src3; local 70 src2.iset(-surf->width() / 2, -surf->height() / 2, 81 canvas->drawImageRect(imgG, src2, dst2, usePaint ? &paint : nullptr);
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/external/skqp/gm/ |
H A D | image.cpp | 67 SkRect src1, src2, src3; local 69 src2.iset(-surf->width() / 2, -surf->height() / 2, 80 canvas->drawImageRect(imgG, src2, dst2, usePaint ? &paint : nullptr);
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/external/swiftshader/src/OpenGL/compiler/ |
H A D | OutputASM.h | 269 Instruction *emit(sw::Shader::Opcode op, TIntermTyped *dst = 0, TIntermNode *src0 = 0, TIntermNode *src1 = 0, TIntermNode *src2 = 0, TIntermNode *src3 = 0, TIntermNode *src4 = 0); 271 TIntermNode *src2 = 0, int index2 = 0, TIntermNode *src3 = 0, int index3 = 0, TIntermNode *src4 = 0, int index4 = 0); 274 void emitBinary(sw::Shader::Opcode op, TIntermTyped *dst = 0, TIntermNode *src0 = 0, TIntermNode *src1 = 0, TIntermNode *src2 = 0);
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/external/webp/src/dsp/ |
H A D | dsp.h | 307 const uint8_t* src2, int stride2, 313 // 8 rows at offset src1 and src2 315 const uint8_t* src2, int stride2); 323 const uint8_t* src2, int len);
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/external/mesa3d/src/gallium/drivers/svga/ |
H A D | svga_tgsi_insn.c | 384 struct src_register src2) 390 emit_src(emit, src2)); 401 struct src_register src2, 408 emit_src(emit, src2) && 578 struct src_register src2) 590 type2 = SVGA3dShaderGetRegType( src2.base.value ); 595 (type2 == SVGA3DREG_CONST && src0.base.num != src2.base.num))) 599 (type2 == SVGA3DREG_CONST && src1.base.num != src2.base.num)) 605 (type2 == SVGA3DREG_INPUT && src0.base.num != src2.base.num))) 609 (type2 == SVGA3DREG_INPUT && src1.base.num != src2 379 emit_op3(struct svga_shader_emitter *emit, SVGA3dShaderInstToken inst, SVGA3dShaderDestToken dest, struct src_register src0, struct src_register src1, struct src_register src2) argument 396 emit_op4(struct svga_shader_emitter *emit, SVGA3dShaderInstToken inst, SVGA3dShaderDestToken dest, struct src_register src0, struct src_register src1, struct src_register src2, struct src_register src3) argument 573 submit_op3(struct svga_shader_emitter *emit, SVGA3dShaderInstToken inst, SVGA3dShaderDestToken dest, struct src_register src0, struct src_register src1, struct src_register src2) argument 645 submit_op4(struct svga_shader_emitter *emit, SVGA3dShaderInstToken inst, SVGA3dShaderDestToken dest, struct src_register src0, struct src_register src1, struct src_register src2, struct src_register src3) argument 1643 const struct src_register src2 = local 2293 submit_lrp(struct svga_shader_emitter *emit, SVGA3dShaderDestToken dst, struct src_register src0, struct src_register src1, struct src_register src2) argument 2340 const struct src_register src2 = translate_src_register( local [all...] |
/external/swiftshader/src/Shader/ |
H A D | PixelPipeline.cpp | 89 const Src &src2 = instruction->src[2]; local 102 if(src2.type != Shader::PARAMETER_VOID) s2 = fetchRegister(src2); 1474 void PixelPipeline::MAD(Vector4s &dst, Vector4s &src0, Vector4s &src1, Vector4s &src2) 1477 { dst.x = MulHigh(src0.x, src1.x); dst.x = AddSat(dst.x, dst.x); dst.x = AddSat(dst.x, dst.x); dst.x = AddSat(dst.x, dst.x); dst.x = AddSat(dst.x, dst.x); dst.x = AddSat(dst.x, src2.x); } 1478 { dst.y = MulHigh(src0.y, src1.y); dst.y = AddSat(dst.y, dst.y); dst.y = AddSat(dst.y, dst.y); dst.y = AddSat(dst.y, dst.y); dst.y = AddSat(dst.y, dst.y); dst.y = AddSat(dst.y, src2.y); } 1479 { dst.z = MulHigh(src0.z, src1.z); dst.z = AddSat(dst.z, dst.z); dst.z = AddSat(dst.z, dst.z); dst.z = AddSat(dst.z, dst.z); dst.z = AddSat(dst.z, dst.z); dst.z = AddSat(dst.z, src2.z); } 1480 { dst.w = MulHigh(src0.w, src1.w); dst.w = AddSat(dst.w, dst.w); dst.w = AddSat(dst.w, dst.w); dst.w = AddSat(dst.w, dst.w); dst.w = AddSat(dst.w, dst.w); dst.w = AddSat(dst.w, src2.w); } 1530 void PixelPipeline::LRP(Vector4s &dst, Vector4s &src0, Vector4s &src1, Vector4s &src2) 1533 { dst.x = SubSat(src1.x, src2 [all...] |
/external/mesa3d/src/mesa/drivers/dri/r200/ |
H A D | r200_vertprog.h | 10 uint32_t src2; member in struct:__anon17193
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/external/pcre/dist2/src/sljit/ |
H A D | sljitLir.h | 219 (which is the src2 argument of sljit_emit_op2). If another register is 843 If src2 is immediate, src2w is masked by (bit_length - 1). 844 Otherwise, if the content of src2 is outside the range from 0 850 If src2 is immediate, src2w is masked by (bit_length - 1). 851 Otherwise, if the content of src2 is outside the range from 0 857 If src2 is immediate, src2w is masked by (bit_length - 1). 858 Otherwise, if the content of src2 is outside the range from 0 866 sljit_s32 src2, sljit_sw src2w); 932 sljit_s32 src2, sljit_sw src2w); 1025 sljit_s32 src2, sljit_s [all...] |
/external/tensorflow/tensorflow/core/kernels/ |
H A D | mkl_aggregate_ops.cc | 360 MklDnnData<T> src2(&cpu_engine); 415 src2.SetUsrMem(md2, &src2_tensor); 451 src2.CheckReorderToOpMem(srcs_pd[1], &net); 453 inputs.push_back(src2.GetOpMem());
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/external/wpa_supplicant_8/hostapd/src/utils/ |
H A D | common.c | 725 const u8 *src2, size_t src2_len) 741 if (src2) { 743 os_memcpy(res + len, src2, res_len - len); 747 os_memcpy(res + len, src2, src2_len); 723 merge_byte_arrays(u8 *res, size_t res_len, const u8 *src1, size_t src1_len, const u8 *src2, size_t src2_len) argument
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/external/wpa_supplicant_8/src/utils/ |
H A D | common.c | 725 const u8 *src2, size_t src2_len) 741 if (src2) { 743 os_memcpy(res + len, src2, res_len - len); 747 os_memcpy(res + len, src2, src2_len); 723 merge_byte_arrays(u8 *res, size_t res_len, const u8 *src1, size_t src1_len, const u8 *src2, size_t src2_len) argument
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/external/wpa_supplicant_8/wpa_supplicant/src/utils/ |
H A D | common.c | 725 const u8 *src2, size_t src2_len) 741 if (src2) { 743 os_memcpy(res + len, src2, res_len - len); 747 os_memcpy(res + len, src2, src2_len); 723 merge_byte_arrays(u8 *res, size_t res_len, const u8 *src1, size_t src1_len, const u8 *src2, size_t src2_len) argument
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/external/mesa3d/src/mesa/program/ |
H A D | program_parse.y | 85 const struct asm_src_register *src1, const struct asm_src_register *src2); 89 const struct asm_src_register *src1, const struct asm_src_register *src2); 94 const struct asm_src_register *src2); 2065 const struct asm_src_register *src2) 2090 if (src2 != NULL) { 2091 inst->Base.SrcReg[2] = src2->Base; 2092 inst->SrcReg[2] = *src2; 2104 const struct asm_src_register *src2) 2112 asm_instruction_set_operands(inst, dst, src0, src1, src2); 2124 const struct asm_src_register *src2) [all...] |
/external/libvpx/libvpx/vpx_dsp/x86/ |
H A D | inv_wht_sse2.asm | 71 %macro ADD_STORE_4P_2X 5 ; src1, src2, tmp1, tmp2, zero
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/external/mesa3d/src/compiler/nir/ |
H A D | nir_lower_wpos_ytransform.c | 72 nir_cmp(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) argument 74 return nir_bcsel(b, nir_flt(b, src0, nir_imm_float(b, 0.0)), src1, src2);
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/external/opencv/cv/src/ |
H A D | cvfilter.cpp | 1357 const int *src0 = src[-1], *src1 = src[0], *src2 = src[1]; 1361 int s0 = src0[i] + src1[i]*2 + src2[i], 1362 s1 = src0[i+1] + src1[i+1]*2 + src2[i+1]; 1369 const int *src0 = src[-1], *src1 = src[0], *src2 = src[1]; 1373 int s0 = src1[i]*10 + (src0[i] + src2[i])*3, 1374 s1 = src1[i+1]*10 + (src0[i+1] + src2[i+1])*3; 1412 const int *src0 = src[-is_m1_0_1], *src2 = src[is_m1_0_1]; 1416 int s0 = src2[i] - src0[i], s1 = src2[i+1] - src0[i+1]; 1682 const float *src0 = src[-1], *src1 = src[0], *src2 [all...] |
/external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/ |
H A D | StoreTile.h | 662 simd16scalari src2 = _simd16_cvtps_epi32(comp2); // padded byte bbbbbbbbbbbbbbbb local 667 src2 = _simd16_slli_epi32(src2, 16); 670 simd16scalari final = _simd16_or_si(_simd16_or_si(src0, src1), _simd16_or_si(src2, src3)); // 0 1 2 3 4 5 6 7 8 9 A B C D E F 732 __m256i src2 = _simd_cvtps_epi32(vComp2); // padded byte bbbbbbbb local 741 __m128i srcLo2 = _mm256_castsi256_si128(src2); // 000b000b000b000b 746 __m128i srcHi2 = _mm256_extractf128_si256(src2, 1); // 000b000b000b000b 776 src2 = _mm256_slli_si256(src2, 2); 780 src2 836 simd16scalari src2 = _simd16_cvtps_epi32(comp2); // padded byte bbbbbbbbbbbbbbbb local 898 __m256i src2 = _simd_cvtps_epi32(vComp2); // padded byte bbbbbbbb local [all...] |
/external/opencv/cxcore/src/ |
H A D | cxmatrix.cpp | 1219 CvMat bstub, *src2 = (CvMat*)b; local 1225 if( !CV_IS_MAT( src2 )) 1226 CV_CALL( src2 = cvGetMat( src2, &bstub )); 1233 icvLSQ( src, src2, dst ); 1249 CV_CALL( cvSVBkSb( w, u, v ? v : u, src2, dst, CV_SVD_U_T + CV_SVD_V_T )); 1257 if( !CV_ARE_TYPES_EQ( src, dst ) || !CV_ARE_TYPES_EQ( src, src2 )) 1263 if( !CV_ARE_SIZES_EQ( src2, dst ) || src->width != src2->height ) 1270 if( src->width <= 3 && src2 [all...] |
/external/libpng/contrib/gregbook/ |
H A D | rpng2-win.c | 1081 uch *src, *src2=NULL, *dest; 1108 src2 = bg_data + row*bg_rowbytes; 1127 bg_red = *src2++; 1128 bg_green = *src2++; 1129 bg_blue = *src2++;
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/external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
H A D | nv50_ir_build_util.cpp | 93 Value *src0, Value *src1, Value *src2) 100 insn->setSrc(2, src2); 224 DataType srcTy, Value *src0, Value *src1, Value *src2) 234 if (src2) 235 insn->setSrc(2, src2); 92 mkOp3(operation op, DataType ty, Value *dst, Value *src0, Value *src1, Value *src2) argument 223 mkCmp(operation op, CondCode cc, DataType dstTy, Value *dst, DataType srcTy, Value *src0, Value *src1, Value *src2) argument
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/external/v8/src/mips64/ |
H A D | macro-assembler-mips64.cc | 94 Register src1, const Operand& src2) { 95 Branch(2, NegateCondition(cond), src1, src2); 110 Register src1, const Operand& src2) { 112 Branch(2, NegateCondition(cond), src1, src2); 4604 DoubleRegister src2) { 4607 if (src2.is(f12)) { 4609 Move(fparg2, src2); 4613 Move(fparg2, src2); 4618 Move(a2, a3, src2); 4621 Move(a3, a2, src2); 91 LoadRoot(Register destination, Heap::RootListIndex index, Condition cond, Register src1, const Operand& src2) argument 107 StoreRoot(Register source, Heap::RootListIndex index, Condition cond, Register src1, const Operand& src2) argument 6183 Float32Max(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) argument 6222 Float32MaxOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) argument 6227 Float32Min(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) argument 6266 Float32MinOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) argument 6271 Float64Max(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) argument 6309 Float64MaxOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) argument 6314 Float64Min(FPURegister dst, FPURegister src1, FPURegister src2, Label* out_of_line) argument 6352 Float64MinOutOfLine(FPURegister dst, FPURegister src1, FPURegister src2) argument [all...] |
/external/capstone/arch/AArch64/ |
H A D | AArch64GenAsmWriter.inc | 7104 // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) 7114 // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) 7127 // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) 7141 // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) 7151 // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) 7164 // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) 7188 // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) 7198 // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) 7211 // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) 7223 // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_exten [all...] |
/external/mesa3d/src/compiler/glsl/ |
H A D | ir_expression_operation.py | 399 src2 = "op[2]->value.{0}[{1}]".format(types[2].union_field, indices[2]) if len(types) >= 3 else "ERROR" 406 src2=src2, 632 operation("fma", 3, source_types=real_types, c_expression="{src0} * {src1} + {src2}"), 634 operation("lrp", 3, source_types=real_types, c_expression={'f': "{src0} * (1.0f - {src2}) + ({src1} * {src2})", 'd': "{src0} * (1.0 - {src2}) + ({src1} * {src2})"}), 644 c_expression="{src0} ? {src1} : {src2}"), 649 c_expression={'u': "bitfield_extract_uint({src0}, {src1}, {src2})", [all...] |