/external/swiftshader/src/Shader/ |
H A D | ShaderCore.cpp | 659 void ShaderCore::add(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 661 dst.x = src0.x + src1.x; 662 dst.y = src0.y + src1.y; 663 dst.z = src0.z + src1.z; 664 dst.w = src0.w + src1.w; 667 void ShaderCore::iadd(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 669 dst.x = As<Float4>(As<Int4>(src0.x) + As<Int4>(src1.x)); 670 dst.y = As<Float4>(As<Int4>(src0.y) + As<Int4>(src1.y)); 671 dst.z = As<Float4>(As<Int4>(src0.z) + As<Int4>(src1.z)); 672 dst.w = As<Float4>(As<Int4>(src0.w) + As<Int4>(src1 675 sub(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 683 isub(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 691 mad(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2) argument 699 imad(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2) argument 707 mul(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 715 imul(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 733 div(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 741 idiv(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 754 udiv(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 767 mod(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 775 imod(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 788 umod(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 801 shl(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 809 ishr(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 817 ushr(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 866 dist1(Float4 &dst, const Vector4f &src0, const Vector4f &src1, bool pp) argument 871 dist2(Float4 &dst, const Vector4f &src0, const Vector4f &src1, bool pp) argument 879 dist3(Float4 &dst, const Vector4f &src0, const Vector4f &src1, bool pp) argument 888 dist4(Float4 &dst, const Vector4f &src0, const Vector4f &src1, bool pp) argument 898 dp1(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 908 dp2(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 918 dp2add(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2) argument 928 dp3(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 938 dp4(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 948 min(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 956 imin(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 964 umin(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 972 max(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 980 imax(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 988 umax(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 996 slt(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1082 att(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1091 lrp(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2) argument 1202 det2(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1208 det3(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2) argument 1214 det4(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2, const Vector4f &src3) argument 1289 powx(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, bool pp) argument 1299 pow(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, bool pp) argument 1307 crs(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1547 atan2(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, bool pp) argument 1652 cmp0(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2) argument 1660 select(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2) argument 1668 extract(Float4 &dst, const Vector4f &src0, const Float4 &src1) argument 1697 cmp0(Float4 &dst, const Float4 &src0, const Float4 &src1, const Float4 &src2) argument 1703 cmp0i(Float4 &dst, const Float4 &src0, const Float4 &src1, const Float4 &src2) argument 1709 select(Float4 &dst, RValue<Int4> src0, const Float4 &src1, const Float4 &src2) argument 1715 cmp(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, Control control) argument 1760 icmp(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, Control control) argument 1805 ucmp(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, Control control) argument 1868 bitwise_or(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1876 bitwise_xor(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1884 bitwise_and(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1892 equal(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument 1903 notEqual(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) argument [all...] |
H A D | ShaderCore.hpp | 233 void add(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); 234 void iadd(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); 235 void sub(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); 236 void isub(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); 237 void mad(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2); 238 void imad(Vector4f &dst, const Vector4f &src0, const Vector4f &src1, const Vector4f &src2); 239 void mul(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); 240 void imul(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); 242 void div(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); 243 void idiv(Vector4f &dst, const Vector4f &src0, const Vector4f &src1); [all...] |
H A D | VertexPipeline.cpp | 937 Float4 VertexPipeline::power(Float4 &src0, Float4 &src1) argument 945 dst *= src1;
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H A D | VertexPipeline.hpp | 41 Float4 power(Float4 &src0, Float4 &src1);
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H A D | VertexProgram.cpp | 130 Src src1 = instruction->src[1]; local 148 if(src1.type != Shader::PARAMETER_VOID) s1 = fetchRegister(src1); 222 case Shader::OPCODE_M3X2: M3X2(d, s0, src1); break; 223 case Shader::OPCODE_M3X3: M3X3(d, s0, src1); break; 224 case Shader::OPCODE_M3X4: M3X4(d, s0, src1); break; 225 case Shader::OPCODE_M4X3: M4X3(d, s0, src1); break; 226 case Shader::OPCODE_M4X4: M4X4(d, s0, src1); break; 310 case Shader::OPCODE_LOOP: LOOP(src1); break; 330 case Shader::OPCODE_TEXLDL: TEXLOD(d, s0, src1, s 954 M3X2(Vector4f &dst, Vector4f &src0, Src &src1) argument 963 M3X3(Vector4f &dst, Vector4f &src0, Src &src1) argument 974 M3X4(Vector4f &dst, Vector4f &src0, Src &src1) argument 987 M4X3(Vector4f &dst, Vector4f &src0, Src &src1) argument 998 M4X4(Vector4f &dst, Vector4f &src0, Src &src1) argument 1016 BREAKC(Vector4f &src0, Vector4f &src1, Control control) argument 1515 TEX(Vector4f &dst, Vector4f &src0, const Src &src1) argument 1520 TEXOFFSET(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &offset) argument 1525 TEXLOD(Vector4f &dst, Vector4f &src0, const Src& src1, Float4 &lod) argument 1530 TEXLODOFFSET(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &offset, Float4 &lod) argument 1535 TEXELFETCH(Vector4f &dst, Vector4f &src0, const Src& src1, Float4 &lod) argument 1540 TEXELFETCHOFFSET(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &offset, Float4 &lod) argument 1545 TEXGRAD(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &dsx, Vector4f &dsy) argument 1550 TEXGRADOFFSET(Vector4f &dst, Vector4f &src0, const Src& src1, Vector4f &dsx, Vector4f &dsy, Vector4f &offset) argument 1555 TEXSIZE(Vector4f &dst, Float4 &lod, const Src &src1) argument [all...] |
H A D | VertexProgram.hpp | 77 void M3X2(Vector4f &dst, Vector4f &src0, Src &src1); 78 void M3X3(Vector4f &dst, Vector4f &src0, Src &src1); 79 void M3X4(Vector4f &dst, Vector4f &src0, Src &src1); 80 void M4X3(Vector4f &dst, Vector4f &src0, Src &src1); 81 void M4X4(Vector4f &dst, Vector4f &src0, Src &src1); 83 void BREAKC(Vector4f &src0, Vector4f &src1, Control); 101 void IFC(Vector4f &src0, Vector4f &src1, Control);
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86GenDAGISel.inc | 2439 /*5380*/ OPC_RecordChild1, // #3 = $src1
2456 // Src: (st (rotl:i8 (ld:i8 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:i8):$src1), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 50
2457 // Dst: (ROL8mi:i32 addr:iPTR:$dst, (imm:i8):$src1)
2462 /*5428*/ OPC_RecordChild1, // #3 = $src1
2479 // Src: (st (rotl:i16 (ld:i16 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi16>>, (imm:i8):$src1), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 50
2480 // Dst: (ROL16mi:i32 addr:iPTR:$dst, (imm:i8):$src1)
2484 /*5475*/ OPC_RecordChild1, // #3 = $src1
2501 // Src: (st (rotl:i32 (ld:i32 addr:iPTR:$dst)<<P:Predicate_unindexedload>><<P:Predicate_loadi32>>, (imm:i8):$src1), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 50
2502 // Dst: (ROL32mi:i32 addr:iPTR:$dst, (imm:i8):$src1)
2506 /*5522*/ OPC_RecordChild1, // #3 = $src1
[all...] |
/external/swiftshader/third_party/subzero/src/ |
H A D | IceTargetLoweringARM32.cpp | 2445 Operand *src1() const { return Src1; } function in class:__anon23512::NumericOperandsBase 3442 ConstantInteger32 *ShAmt = llvm::cast<ConstantInteger32>(Srcs.src1()); 3466 ConstantInteger32 *ShAmt = llvm::cast<ConstantInteger32>(Srcs.src1()); 3491 ConstantInteger32 *ShAmt = llvm::cast<ConstantInteger32>(Srcs.src1());
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/external/tensorflow/tensorflow/core/kernels/ |
H A D | mkl_aggregate_ops.cc | 359 MklDnnData<T> src1(&cpu_engine); 414 src1.SetUsrMem(md1, &src1_tensor); 450 src1.CheckReorderToOpMem(srcs_pd[0], &net); 452 inputs.push_back(src1.GetOpMem());
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/external/v8/src/arm/ |
H A D | assembler-arm.cc | 1509 void Assembler::and_(Register dst, Register src1, const Operand& src2, argument 1511 addrmod1(cond | AND | s, src1, dst, src2); 1515 void Assembler::eor(Register dst, Register src1, const Operand& src2, argument 1517 addrmod1(cond | EOR | s, src1, dst, src2); 1521 void Assembler::sub(Register dst, Register src1, const Operand& src2, argument 1523 addrmod1(cond | SUB | s, src1, dst, src2); 1527 void Assembler::rsb(Register dst, Register src1, const Operand& src2, argument 1529 addrmod1(cond | RSB | s, src1, dst, src2); 1533 void Assembler::add(Register dst, Register src1, const Operand& src2, argument 1535 addrmod1(cond | ADD | s, src1, ds 1539 adc(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) argument 1545 sbc(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) argument 1551 rsc(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) argument 1557 tst(Register src1, const Operand& src2, Condition cond) argument 1562 teq(Register src1, const Operand& src2, Condition cond) argument 1567 cmp(Register src1, const Operand& src2, Condition cond) argument 1579 cmn(Register src1, const Operand& src2, Condition cond) argument 1584 orr(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) argument 1650 bic(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) argument 1662 mla(Register dst, Register src1, Register src2, Register srcA, SBit s, Condition cond) argument 1670 mls(Register dst, Register src1, Register src2, Register srcA, Condition cond) argument 1679 sdiv(Register dst, Register src1, Register src2, Condition cond) argument 1688 udiv(Register dst, Register src1, Register src2, Condition cond) argument 1697 mul(Register dst, Register src1, Register src2, SBit s, Condition cond) argument 1705 smmla(Register dst, Register src1, Register src2, Register srcA, Condition cond) argument 1713 smmul(Register dst, Register src1, Register src2, Condition cond) argument 1721 smlal(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) argument 1734 smull(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) argument 1747 umlal(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) argument 1760 umull(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) argument 1875 pkhbt(Register dst, Register src1, const Operand& src2, Condition cond ) argument 1894 pkhtb(Register dst, Register src1, const Operand& src2, Condition cond) argument 1926 sxtab(Register dst, Register src1, Register src2, int rotate, Condition cond) argument 1952 sxtah(Register dst, Register src1, Register src2, int rotate, Condition cond) argument 1978 uxtab(Register dst, Register src1, Register src2, int rotate, Condition cond) argument 2016 uxtah(Register dst, Register src1, Register src2, int rotate, Condition cond) argument 2123 strd(Register src1, Register src2, const MemOperand& dst, Condition cond) argument 2139 strex(Register src1, Register src2, Register dst, Condition cond) argument 2155 strexb(Register src1, Register src2, Register dst, Condition cond) argument 2171 strexh(Register src1, Register src2, Register dst, Condition cond) argument 2891 vmov(const DwVfpRegister dst, const Register src1, const Register src2, const Condition cond) argument 3228 vadd(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3251 vadd(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3269 vsub(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3292 vsub(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3310 vmul(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3333 vmul(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3351 vmla(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3372 vmla(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3388 vmls(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3409 vmls(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3425 vdiv(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3448 vdiv(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3466 vcmp(const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3484 vcmp(const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3499 vcmp(const DwVfpRegister src1, const double src2, const Condition cond) argument 3514 vcmp(const SwVfpRegister src1, const float src2, const Condition cond) argument 3527 vmaxnm(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2) argument 3543 vmaxnm(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2) argument 3559 vminnm(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2) argument 3575 vminnm(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2) argument 3591 vsel(Condition cond, const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2) argument 3623 vsel(Condition cond, const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2) argument 4121 veor(DwVfpRegister dst, DwVfpRegister src1, DwVfpRegister src2) argument 4138 EncodeNeonBinaryBitwiseOp(BinaryBitwiseOp op, const QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4182 vand(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4190 vbsl(QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4198 veor(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4206 vorr(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4227 EncodeNeonBinOp(FPBinOp op, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4289 EncodeNeonBinOp(IntegerBinOp op, NeonDataType dt, const QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4344 EncodeNeonBinOp(IntegerBinOp op, NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4353 vadd(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4361 vadd(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4369 vqadd(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4377 vsub(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4385 vsub(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4393 vqsub(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4401 vmul(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4409 vmul(NeonSize size, QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4417 vmin(const QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4425 vmin(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4433 vmax(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4441 vmax(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4516 vrecps(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4524 vrsqrts(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4532 vtst(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4540 vceq(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4548 vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4556 vcge(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4564 vcge(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4572 vcgt(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4580 vcgt(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4588 vext(QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2, int bytes) argument [all...] |
H A D | assembler-arm.h | 808 void and_(Register dst, Register src1, const Operand& src2, 811 void eor(Register dst, Register src1, const Operand& src2, 814 void sub(Register dst, Register src1, const Operand& src2, 816 void sub(Register dst, Register src1, Register src2, 818 sub(dst, src1, Operand(src2), s, cond); 821 void rsb(Register dst, Register src1, const Operand& src2, 824 void add(Register dst, Register src1, const Operand& src2, 826 void add(Register dst, Register src1, Register src2, 828 add(dst, src1, Operand(src2), s, cond); 831 void adc(Register dst, Register src1, cons [all...] |
H A D | macro-assembler-arm.cc | 296 void MacroAssembler::Mls(Register dst, Register src1, Register src2, argument 300 mls(dst, src1, src2, srcA, cond); 303 mul(ip, src1, src2, LeaveCC, cond); 309 void MacroAssembler::And(Register dst, Register src1, const Operand& src2, argument 320 ubfx(dst, src1, 0, 323 and_(dst, src1, src2, LeaveCC, cond); 328 void MacroAssembler::Ubfx(Register dst, Register src1, int lsb, int width, argument 333 and_(dst, src1, Operand(mask), LeaveCC, cond); 339 ubfx(dst, src1, lsb, width, cond); 344 void MacroAssembler::Sbfx(Register dst, Register src1, in 3399 MovToFloatParameters(DwVfpRegister src1, DwVfpRegister src2) argument [all...] |
H A D | macro-assembler-arm.h | 152 void Mls(Register dst, Register src1, Register src2, Register srcA, 154 void And(Register dst, Register src1, const Operand& src2, 337 void Push(Register src1, Register src2, Condition cond = al) { argument 338 if (src1.code() > src2.code()) { 339 stm(db_w, sp, src1.bit() | src2.bit(), cond); 341 str(src1, MemOperand(sp, 4, NegPreIndex), cond); 347 void Push(Register src1, Register src2, Register src3, Condition cond = al) { argument 348 if (src1.code() > src2.code()) { 350 stm(db_w, sp, src1.bit() | src2.bit() | src3.bit(), cond); 352 stm(db_w, sp, src1 362 Push(Register src1, Register src2, Register src3, Register src4, Condition cond = al) argument 389 Push(Register src1, Register src2, Register src3, Register src4, Register src5, Condition cond = al) argument 418 Pop(Register src1, Register src2, Condition cond = al) argument 429 Pop(Register src1, Register src2, Register src3, Condition cond = al) argument 445 Pop(Register src1, Register src2, Register src3, Register src4, Condition cond = al) argument [all...] |
H A D | simulator-arm.cc | 4011 T src1[kLanes], src2[kLanes]; local 4012 simulator->get_q_register(Vn, src1); 4015 src1[i] = Clamp<T>(Widen(src1[i]) + Widen(src2[i])); 4017 simulator->set_q_register(Vd, src1); 4023 T src1[kLanes], src2[kLanes]; local 4024 simulator->get_q_register(Vn, src1); 4027 src1[i] = Clamp<T>(Widen(src1[i]) - Widen(src2[i])); 4029 simulator->set_q_register(Vd, src1); 4074 uint32_t src1[4]; local 4087 uint32_t src1[4], src2[4]; local 4128 int8_t src1[16], src2[16]; local 4141 int16_t src1[8], src2[8]; local 4154 int32_t src1[4], src2[4]; local 4178 int8_t src1[16], src2[16]; local 4191 int16_t src1[8], src2[8]; local 4204 int32_t src1[4], src2[4]; local 4229 uint8_t src1[16], src2[16]; local 4239 uint16_t src1[8], src2[8]; local 4249 uint32_t src1[4], src2[4]; local 4266 uint8_t src1[16], src2[16]; local 4276 uint16_t src1[8], src2[8]; local 4286 uint32_t src1[4], src2[4]; local 4308 uint8_t src1[16], src2[16]; local 4318 uint16_t src1[8], src2[8]; local 4328 uint32_t src1[4], src2[4]; local 4348 float src1[4], src2[4]; local 4369 float src1[4], src2[4]; local 4384 float src1[4], src2[4]; local 4450 uint8_t src1[16], src2[16], dst[16]; local 4582 uint32_t dst[4], src1[4], src2[4]; local 4593 uint64_t src1, src2; local 4601 uint32_t src1[4], src2[4]; local 4641 uint8_t src1[16], src2[16]; local 4654 uint16_t src1[8], src2[8]; local 4667 uint32_t src1[4], src2[4]; local 4691 uint8_t src1[16], src2[16]; local 4704 uint16_t src1[8], src2[8]; local 4717 uint32_t src1[4], src2[4]; local 4741 uint8_t src1[16], src2[16]; local 4751 uint16_t src1[8], src2[8]; local 4761 uint32_t src1[4], src2[4]; local 4779 uint8_t src1[16], src2[16]; local 4789 uint16_t src1[8], src2[8]; local 4799 uint32_t src1[4], src2[4]; local 4818 float src1[4], src2[4]; local 4834 float src1[4], src2[4]; local 4979 uint8_t src1[16], src2[16], dst1[16], dst2[16]; local 4993 uint16_t src1[8], src2[8], dst1[8], dst2[8]; local 5007 uint32_t src1[4], src2[4], dst1[4], dst2[4]; local [all...] |
/external/v8/src/arm64/ |
H A D | macro-assembler-arm64-inl.h | 1351 void MacroAssembler::SmiTagAndPush(Register src1, Register src2) { argument 1355 Push(src1.W(), wzr, src2.W(), wzr);
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H A D | macro-assembler-arm64.cc | 868 void MacroAssembler::Push(const CPURegister& src0, const CPURegister& src1, argument 870 DCHECK(AreSameSizeAndType(src0, src1, src2, src3)); 872 int count = 1 + src1.IsValid() + src2.IsValid() + src3.IsValid(); 876 PushHelper(count, size, src0, src1, src2, src3); 880 void MacroAssembler::Push(const CPURegister& src0, const CPURegister& src1, argument 884 DCHECK(AreSameSizeAndType(src0, src1, src2, src3, src4, src5, src6, src7)); 890 PushHelper(4, size, src0, src1, src2, src3); 930 void MacroAssembler::Push(const Register& src0, const FPRegister& src1) { argument 931 int size = src0.SizeInBytes() + src1.SizeInBytes(); 934 // Reserve room for src0 and push src1 1003 const CPURegister& src1 = registers.PopHighestIndex(); local 1115 PushHelper(int count, int size, const CPURegister& src0, const CPURegister& src1, const CPURegister& src2, const CPURegister& src3) argument 1260 PokePair(const CPURegister& src1, const CPURegister& src2, int offset) argument [all...] |
H A D | macro-assembler-arm64.h | 609 void Push(const CPURegister& src0, const CPURegister& src1 = NoReg, 611 void Push(const CPURegister& src0, const CPURegister& src1, 621 void Push(const Register& src0, const FPRegister& src1); 730 // Poke 'src1' and 'src2' onto the stack. The values written will be adjacent 731 // with 'src2' at a higher address than 'src1'. The offset is in bytes. 735 void PokePair(const CPURegister& src1, const CPURegister& src2, int offset); 979 inline void SmiTagAndPush(Register src1, Register src2); 1936 const CPURegister& src0, const CPURegister& src1,
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/external/v8/src/compiler/ia32/ |
H A D | code-generator-ia32.cc | 2579 Operand src1 = g.ToOperand(source); local 2580 __ push(src1); 2618 Operand src1 = g.HighOperand(source); local 2623 __ push(src1);
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/external/v8/src/compiler/mips/ |
H A D | code-generator-mips.cc | 276 ool_name(CodeGenerator* gen, T dst, T src1, T src2) \ 277 : OutOfLineCode(gen), dst_(dst), src1_(src1), src2_(src2) {} \ 1249 FPURegister src1 = i.InputSingleRegister(0); local 1251 auto ool = new (zone()) OutOfLineFloat32Max(this, dst, src1, src2); 1252 __ Float32Max(dst, src1, src2, ool->entry()); 1258 DoubleRegister src1 = i.InputDoubleRegister(0); local 1260 auto ool = new (zone()) OutOfLineFloat64Max(this, dst, src1, src2); 1261 __ Float64Max(dst, src1, src2, ool->entry()); 1267 FPURegister src1 = i.InputSingleRegister(0); local 1269 auto ool = new (zone()) OutOfLineFloat32Min(this, dst, src1, src 1276 DoubleRegister src1 = i.InputDoubleRegister(0); local [all...] |
/external/v8/src/compiler/mips64/ |
H A D | code-generator-mips64.cc | 276 ool_name(CodeGenerator* gen, T dst, T src1, T src2) \ 277 : OutOfLineCode(gen), dst_(dst), src1_(src1), src2_(src2) {} \ 1463 FPURegister src1 = i.InputSingleRegister(0); local 1465 auto ool = new (zone()) OutOfLineFloat32Max(this, dst, src1, src2); 1466 __ Float32Max(dst, src1, src2, ool->entry()); 1472 FPURegister src1 = i.InputDoubleRegister(0); local 1474 auto ool = new (zone()) OutOfLineFloat64Max(this, dst, src1, src2); 1475 __ Float64Max(dst, src1, src2, ool->entry()); 1481 FPURegister src1 = i.InputSingleRegister(0); local 1483 auto ool = new (zone()) OutOfLineFloat32Min(this, dst, src1, src 1490 FPURegister src1 = i.InputDoubleRegister(0); local [all...] |
/external/v8/src/compiler/x87/ |
H A D | code-generator-x87.cc | 2695 Operand src1 = g.ToOperand(source); local 2696 __ push(src1);
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/external/v8/src/crankshaft/ia32/ |
H A D | lithium-gap-resolver-ia32.cc | 439 Operand src1 = cgen_->HighOperand(source); local 445 __ mov(tmp, src1);
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/external/v8/src/crankshaft/mips/ |
H A D | lithium-codegen-mips.cc | 774 Register src1, const Operand& src2) { 808 __ Branch(&skip, NegateCondition(condition), src1, src2); 822 __ Call(entry, RelocInfo::RUNTIME_ENTRY, condition, src1, src2); 833 __ Branch(&jump_table_.last().label, condition, src1, src2); 838 DeoptimizeReason deopt_reason, Register src1, 843 DeoptimizeIf(condition, instr, deopt_reason, bailout_type, src1, src2); 1847 Register src1, 1857 NegateCondition(condition), src1, src2); 1859 __ Branch(chunk_->GetAssemblyLabel(left_block), condition, src1, src2); 1861 __ Branch(chunk_->GetAssemblyLabel(left_block), condition, src1, src 771 DeoptimizeIf(Condition condition, LInstruction* instr, DeoptimizeReason deopt_reason, Deoptimizer::BailoutType bailout_type, Register src1, const Operand& src2) argument 837 DeoptimizeIf(Condition condition, LInstruction* instr, DeoptimizeReason deopt_reason, Register src1, const Operand& src2) argument 1845 EmitBranch(InstrType instr, Condition condition, Register src1, const Operand& src2) argument 1868 EmitBranchF(InstrType instr, Condition condition, FPURegister src1, FPURegister src2) argument 1893 EmitTrueBranch(InstrType instr, Condition condition, Register src1, const Operand& src2) argument 1901 EmitFalseBranch(InstrType instr, Condition condition, Register src1, const Operand& src2) argument 1909 EmitFalseBranchF(InstrType instr, Condition condition, FPURegister src1, FPURegister src2) argument [all...] |
H A D | lithium-codegen-mips.h | 230 Register src1 = zero_reg, 234 Register src1 = zero_reg, 272 Register src1, 277 FPURegister src1, 280 void EmitTrueBranch(InstrType instr, Condition condition, Register src1, 283 void EmitFalseBranch(InstrType instr, Condition condition, Register src1, 288 FPURegister src1,
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/external/v8/src/crankshaft/mips64/ |
H A D | lithium-codegen-mips64.cc | 762 Register src1, const Operand& src2) { 796 __ Branch(&skip, NegateCondition(condition), src1, src2); 810 __ Call(entry, RelocInfo::RUNTIME_ENTRY, condition, src1, src2); 822 __ Branch(&jump_table_.last()->label, condition, src1, src2); 827 DeoptimizeReason deopt_reason, Register src1, 832 DeoptimizeIf(condition, instr, deopt_reason, bailout_type, src1, src2); 1968 Register src1, 1978 NegateCondition(condition), src1, src2); 1980 __ Branch(chunk_->GetAssemblyLabel(left_block), condition, src1, src2); 1982 __ Branch(chunk_->GetAssemblyLabel(left_block), condition, src1, src 759 DeoptimizeIf(Condition condition, LInstruction* instr, DeoptimizeReason deopt_reason, Deoptimizer::BailoutType bailout_type, Register src1, const Operand& src2) argument 826 DeoptimizeIf(Condition condition, LInstruction* instr, DeoptimizeReason deopt_reason, Register src1, const Operand& src2) argument 1966 EmitBranch(InstrType instr, Condition condition, Register src1, const Operand& src2) argument 1989 EmitBranchF(InstrType instr, Condition condition, FPURegister src1, FPURegister src2) argument 2014 EmitTrueBranch(InstrType instr, Condition condition, Register src1, const Operand& src2) argument 2022 EmitFalseBranch(InstrType instr, Condition condition, Register src1, const Operand& src2) argument 2030 EmitFalseBranchF(InstrType instr, Condition condition, FPURegister src1, FPURegister src2) argument [all...] |