Searched refs:reg2 (Results 1 - 14 of 14) sorted by relevance

/art/runtime/interpreter/mterp/arm64/
H A Dheader.S302 .macro SAVE_TWO_REGS reg1, reg2, offset
303 stp \reg1, \reg2, [sp, #(\offset)]
305 .cfi_rel_offset \reg2, (\offset) + 8
311 .macro RESTORE_TWO_REGS reg1, reg2, offset
312 ldp \reg1, \reg2, [sp, #(\offset)]
314 .cfi_restore \reg2
320 .macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment
321 stp \reg1, \reg2, [sp, #-(\frame_adjustment)]!
324 .cfi_rel_offset \reg2, 8
330 .macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustmen
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/art/compiler/utils/
H A Dassembler_test.h194 for (auto reg2 : reg2_registers) {
198 (assembler_.get()->*f)(*reg1, *reg2, new_imm * multiplier + bias);
208 std::string reg2_string = (this->*GetName2)(*reg2);
249 for (auto reg2 : reg2_registers) {
254 (assembler_.get()->*f)(*reg1, *reg2, *reg3, new_imm + bias);
264 std::string reg2_string = (this->*GetName2)(*reg2);
311 for (auto reg2 : reg2_registers) {
315 (assembler_.get()->*f)(new_imm, *reg1, *reg2);
325 std::string reg2_string = (this->*GetName2)(*reg2);
1319 for (auto reg2
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/art/runtime/arch/arm64/
H A Dquick_entrypoints_arm64.S55 .macro SAVE_TWO_REGS reg1, reg2, offset
56 stp \reg1, \reg2, [sp, #(\offset)]
58 .cfi_rel_offset \reg2, (\offset) + 8
61 .macro RESTORE_TWO_REGS reg1, reg2, offset
62 ldp \reg1, \reg2, [sp, #(\offset)]
64 .cfi_restore \reg2
67 .macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment
68 stp \reg1, \reg2, [sp, #-(\frame_adjustment)]!
71 .cfi_rel_offset \reg2, 8
74 .macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustmen
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/art/compiler/utils/mips64/
H A Dassembler_mips64_test.cc416 DriverStr(RepeatFFF(&mips64::Mips64Assembler::AddS, "add.s ${reg1}, ${reg2}, ${reg3}"), "add.s");
420 DriverStr(RepeatFFF(&mips64::Mips64Assembler::AddD, "add.d ${reg1}, ${reg2}, ${reg3}"), "add.d");
424 DriverStr(RepeatFFF(&mips64::Mips64Assembler::SubS, "sub.s ${reg1}, ${reg2}, ${reg3}"), "sub.s");
428 DriverStr(RepeatFFF(&mips64::Mips64Assembler::SubD, "sub.d ${reg1}, ${reg2}, ${reg3}"), "sub.d");
432 DriverStr(RepeatFFF(&mips64::Mips64Assembler::MulS, "mul.s ${reg1}, ${reg2}, ${reg3}"), "mul.s");
436 DriverStr(RepeatFFF(&mips64::Mips64Assembler::MulD, "mul.d ${reg1}, ${reg2}, ${reg3}"), "mul.d");
440 DriverStr(RepeatFFF(&mips64::Mips64Assembler::DivS, "div.s ${reg1}, ${reg2}, ${reg3}"), "div.s");
444 DriverStr(RepeatFFF(&mips64::Mips64Assembler::DivD, "div.d ${reg1}, ${reg2}, ${reg3}"), "div.d");
448 DriverStr(RepeatFF(&mips64::Mips64Assembler::SqrtS, "sqrt.s ${reg1}, ${reg2}"), "sqrt.s");
452 DriverStr(RepeatFF(&mips64::Mips64Assembler::SqrtD, "sqrt.d ${reg1}, ${reg2}"), "sqr
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/art/runtime/interpreter/mterp/out/
H A Dmterp_arm64.S309 .macro SAVE_TWO_REGS reg1, reg2, offset
310 stp \reg1, \reg2, [sp, #(\offset)]
312 .cfi_rel_offset \reg2, (\offset) + 8
318 .macro RESTORE_TWO_REGS reg1, reg2, offset
319 ldp \reg1, \reg2, [sp, #(\offset)]
321 .cfi_restore \reg2
327 .macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment
328 stp \reg1, \reg2, [sp, #-(\frame_adjustment)]!
331 .cfi_rel_offset \reg2, 8
337 .macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustmen
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/art/compiler/optimizing/
H A Dcode_generator_x86_64.h142 void Exchange64(CpuRegister reg1, CpuRegister reg2);
H A Dcode_generator_arm_vixl.cc4651 vixl32::Register reg2 = RegisterFrom(second); local
4654 // temp = reg1 / reg2 (integer division)
4655 // dest = reg1 - temp * reg2
4656 __ Sdiv(temp, reg1, reg2);
4657 __ Mls(out_reg, temp, reg2, reg1);
H A Dcode_generator_x86_64.cc5333 void ParallelMoveResolverX86_64::Exchange64(CpuRegister reg1, CpuRegister reg2) { argument
5335 __ movq(reg1, reg2);
5336 __ movq(reg2, CpuRegister(TMP));
/art/compiler/utils/x86_64/
H A Dassembler_x86_64.h660 void testl(CpuRegister reg1, CpuRegister reg2);
664 void testq(CpuRegister reg1, CpuRegister reg2);
H A Dassembler_x86_64.cc2294 void X86_64Assembler::testl(CpuRegister reg1, CpuRegister reg2) { argument
2296 EmitOptionalRex32(reg1, reg2);
2298 EmitRegisterOperand(reg1.LowBits(), reg2.LowBits());
2336 void X86_64Assembler::testq(CpuRegister reg1, CpuRegister reg2) { argument
2338 EmitRex64(reg1, reg2);
2340 EmitRegisterOperand(reg1.LowBits(), reg2.LowBits());
/art/compiler/utils/mips/
H A Dassembler_mips_test.cc349 DriverStr(RepeatRRR(&mips::MipsAssembler::Addu, "addu ${reg1}, ${reg2}, ${reg3}"), "Addu");
353 DriverStr(RepeatRRIb(&mips::MipsAssembler::Addiu, -16, "addiu ${reg1}, ${reg2}, {imm}"), "Addiu");
357 DriverStr(RepeatRRR(&mips::MipsAssembler::Subu, "subu ${reg1}, ${reg2}, ${reg3}"), "Subu");
361 DriverStr(RepeatRR(&mips::MipsAssembler::MultR2, "mult ${reg1}, ${reg2}"), "MultR2");
365 DriverStr(RepeatRR(&mips::MipsAssembler::MultuR2, "multu ${reg1}, ${reg2}"), "MultuR2");
369 DriverStr(RepeatRR(&mips::MipsAssembler::DivR2, "div $zero, ${reg1}, ${reg2}"), "DivR2Basic");
373 DriverStr(RepeatRR(&mips::MipsAssembler::DivuR2, "divu $zero, ${reg1}, ${reg2}"), "DivuR2Basic");
377 DriverStr(RepeatRRR(&mips::MipsAssembler::MulR2, "mul ${reg1}, ${reg2}, ${reg3}"), "MulR2");
381 DriverStr(RepeatRRR(&mips::MipsAssembler::DivR2, "div $zero, ${reg2}, ${reg3}\nmflo ${reg1}"),
386 DriverStr(RepeatRRR(&mips::MipsAssembler::ModR2, "div $zero, ${reg2},
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/art/runtime/arch/mips/
H A Dquick_entrypoints_mips.S915 .macro LOAD_LONG_TO_REG reg1, reg2, next_arg, index_reg, next_index, label
917 lw $\reg2, -4($\next_arg)
932 .macro LOAD_DOUBLE_TO_REG reg1, reg2, next_arg, index_reg, tmp, label
934 LDu $\reg1, $\reg2, -8, $\next_arg, $\tmp # next_arg points to argument after the current one
942 .macro LOAD_DOUBLE_TO_REG reg1, reg2, next_arg, index_reg, tmp, label
943 LDu $\reg1, $\reg2, -8, $\next_arg, $\tmp # next_arg points to argument after the current one
/art/compiler/utils/x86/
H A Dassembler_x86.h612 void testl(Register reg1, Register reg2);
H A Dassembler_x86.cc1968 void X86Assembler::testl(Register reg1, Register reg2) { argument
1971 EmitRegisterOperand(reg1, reg2);

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