Searched refs:CSEL (Results 1 - 9 of 9) sorted by relevance
| /external/llvm/test/MC/AArch64/ |
| H A D | arm64-arithmetic-encoding.s | 569 CSEL W16, W7, W27, EQ
570 CSEL W15, W6, W26, NE
571 CSEL W14, W5, W25, CS
572 CSEL W13, W4, W24, HS
578 CSEL X7, X7, X3, VC
579 CSEL X6, X7, X4, HI
580 CSEL X5, X6, X5, LS
581 CSEL X4, X5, X6, GE
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| H A D | brw_fs_builder.h | 462 ALU3(CSEL)
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| H A D | brw_vec4_builder.h | 408 ALU3(CSEL)
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 43 CSEL,
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| H A D | AArch64ISelLowering.cpp | 743 case AArch64ISD::CSEL: {
842 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
1788 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1850 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
3888 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3894 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3907 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3911 // this case, we emit the first CSEL and then emit a second using the output
3917 DAG.getNode(AArch64ISD::CSEL, d
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| /external/v8/src/arm64/ |
| H A D | constants-arm64.h | 919 CSEL = CSEL_w, enumerator in enum:v8::internal::ConditionalSelectOp
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| H A D | assembler-arm64.cc | 1333 ConditionalSelect(rd, rn, rm, cond, CSEL);
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| /external/vixl/src/aarch64/ |
| H A D | constants-aarch64.h | 1013 CSEL = CSEL_w, enumerator in enum:vixl::aarch64::ConditionalSelectOp
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| H A D | assembler-aarch64.cc | 640 ConditionalSelect(rd, rn, rm, cond, CSEL);
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