| /external/shaderc/spirv-headers/include/spirv/1.0/ |
| H A D | OpenCL.std.h | 201 Clz = 151, enumerator in enum:OpenCLLIB::Entrypoints
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| /external/shaderc/spirv-headers/include/spirv/1.1/ |
| H A D | OpenCL.std.h | 201 Clz = 151, enumerator in enum:OpenCLLIB::Entrypoints
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| /external/spirv-llvm/lib/SPIRV/libSPIRV/ |
| H A D | OpenCL.std.h | 201 Clz = 151, enumerator in enum:OpenCLLIB::Entrypoints
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| H A D | SPIRVExtInst.h | 212 add(OpenCLLIB::Clz, "clz");
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| /external/v8/src/wasm/ |
| H A D | wasm-opcodes.cc | 66 CASE_INT_OP(Clz, "clz")
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| /external/v8/src/compiler/ |
| H A D | machine-operator.h | 643 V(Word, Clz) \
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| /external/swiftshader/third_party/subzero/src/ |
| H A D | IceInstMIPS32.h | 214 Clz, enumerator in enum:Ice::MIPS32::InstMIPS32::InstKindMIPS32
1221 using InstMIPS32Clz = InstMIPS32TwoAddrGPR<InstMIPS32::Clz>;
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| H A D | IceInstARM32.h | 388 Clz, enumerator in enum:Ice::ARM32::InstARM32::InstKindARM32
1054 using InstARM32Clz = InstARM32UnaryopGPR<InstARM32::Clz, false>;
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| H A D | IceInstARM32.cpp | 3526 template class InstARM32UnaryopGPR<InstARM32::Clz, false>;
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| /external/vixl/test/aarch32/ |
| H A D | test-macro-assembler-cond-rd-rn-a32.cc | 56 M(Clz) \
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| H A D | test-macro-assembler-cond-rd-rn-t32.cc | 56 M(Clz) \
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| H A D | test-disasm-a32.cc | 2724 MUST_FAIL_TEST_BOTH(Clz(pc, r0), "Unpredictable instruction.\n");
2725 MUST_FAIL_TEST_BOTH(Clz(r0, pc), "Unpredictable instruction.\n");
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| H A D | test-simulator-cond-rd-rn-a32.cc | 116 M(Clz) \
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| H A D | test-simulator-cond-rd-rn-t32.cc | 116 M(Clz) \
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| /external/v8/src/compiler/arm64/ |
| H A D | code-generator-arm64.cc | 1257 __ Clz(i.OutputRegister64(), i.InputRegister64(0));
1260 __ Clz(i.OutputRegister32(), i.InputRegister32(0));
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| /external/v8/src/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 438 void MacroAssembler::Clz(const Register& rd, const Register& rn) { function in class:v8::internal::MacroAssembler
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| H A D | macro-assembler-arm64.h | 369 inline void Clz(const Register& rd, const Register& rn);
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| /external/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 1098 void Clz(const Register& rd, const Register& rn) { function in class:vixl::aarch64::MacroAssembler
2302 V(clz, Clz) \
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| /external/v8/src/mips/ |
| H A D | macro-assembler-mips.h | 314 void Clz(Register rd, Register rs);
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| /external/v8/src/mips64/ |
| H A D | macro-assembler-mips64.h | 347 void Clz(Register rd, Register rs);
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| /external/vixl/test/aarch64/ |
| H A D | test-disasm-aarch64.cc | 5868 COMPARE_MACRO(Clz(v1.V8B(), v8.V8B()),
5871 COMPARE_MACRO(Clz(v2.V16B(), v9.V16B()),
5874 COMPARE_MACRO(Clz(v3.V4H(), v1.V4H()),
5877 COMPARE_MACRO(Clz(v4.V8H(), v2.V8H()),
5880 COMPARE_MACRO(Clz(v5.V2S(), v3.V2S()),
5883 COMPARE_MACRO(Clz(v6.V4S(), v4.V4S()),
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| H A D | test-assembler-aarch64.cc | 1817 __ Clz(w0, w24);
1818 __ Clz(x1, x24);
1819 __ Clz(w2, w25);
1820 __ Clz(x3, x25);
1821 __ Clz(w4, w26);
1822 __ Clz(x5, x26);
19366 __ Clz(v22.V8B(), v0.V8B());
19367 __ Clz(v23.V16B(), v0.V16B());
19368 __ Clz(v24.V4H(), v0.V4H());
19369 __ Clz(v2
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 1246 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); local
1247 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
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| /external/v8/src/compiler/mips/ |
| H A D | code-generator-mips.cc | 913 __ Clz(i.OutputRegister(), i.InputRegister(0));
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| /external/v8/src/compiler/mips64/ |
| H A D | code-generator-mips64.cc | 1034 __ Clz(i.OutputRegister(), i.InputRegister(0));
|