Searched refs:Emit (Results 1 - 25 of 171) sorted by relevance

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/external/llvm/unittests/Bitcode/
H A DBitstreamWriterTest.cpp37 W.Emit('s', 8);
38 W.Emit('t', 8);
39 W.Emit('r', 8);
40 W.Emit(0, 8);
/external/v8/src/regexp/
H A Dregexp-macro-assembler-irregexp.cc74 Emit(BC_POP_REGISTER, register_index);
83 Emit(BC_PUSH_REGISTER, register_index);
91 Emit(BC_SET_REGISTER_TO_CP, register_index);
108 Emit(BC_SET_CP_TO_REGISTER, register_index);
116 Emit(BC_SET_REGISTER_TO_SP, register_index);
124 Emit(BC_SET_SP_TO_REGISTER, register_index);
130 Emit(BC_SET_CURRENT_POSITION_FROM_END, by);
137 Emit(BC_SET_REGISTER, register_index);
145 Emit(BC_ADVANCE_REGISTER, register_index);
151 Emit(BC_POP_C
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/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DR600MCCodeEmitter.cpp55 void Emit(uint32_t value, raw_ostream &OS) const;
56 void Emit(uint64_t value, raw_ostream &OS) const;
103 Emit(InstWord01, OS);
104 Emit(InstWord2, OS);
105 Emit((uint32_t) 0, OS);
127 Emit(Word01, OS);
128 Emit(Word2, OS);
129 Emit((uint32_t) 0, OS);
139 Emit(Inst, OS);
143 void R600MCCodeEmitter::Emit(uint32_ function in class:R600MCCodeEmitter
147 void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const { function in class:R600MCCodeEmitter
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/external/v8/src/compiler/x87/
H A Dinstruction-selector-x87.cc214 Emit(code, 1, outputs, input_count, inputs);
266 Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
316 Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count,
372 Emit(opcode | AddressingModeField::encode(kMode_MRI),
376 Emit(opcode | AddressingModeField::encode(kMode_MR1),
430 Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(),
434 Emit(opcode | AddressingModeField::encode(kMode_MR1), g.NoOutput(),
498 selector->Emit(opcode, output_count, outputs, input_count, inputs);
526 Emit(kX87Not, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()));
541 selector->Emit(opcod
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/external/clang/utils/TableGen/
H A DClangCommentHTMLTagsEmitter.cpp33 StringMatcher("Name", Matches, OS).Emit();
55 StringMatcher("Name", MatchesEndTagOptional, OS).Emit();
60 StringMatcher("Name", MatchesEndTagForbidden, OS).Emit();
H A DClangCommentHTMLNamedCharacterReferenceEmitter.cpp79 StringMatcher("Name", NameToUTF8, OS).Emit();
/external/llvm/include/llvm/TableGen/
H A DStringMatcher.h45 void Emit(unsigned Indent = 0) const;
/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DStringMatcher.h44 void Emit(unsigned Indent = 0) const;
/external/v8/src/compiler/mips/
H A Dinstruction-selector-mips.cc126 selector->Emit(opcode, g.DefineAsRegister(node),
135 selector->Emit(opcode, g.DefineAsRegister(node),
143 selector->Emit(opcode, g.DefineAsRegister(node),
216 selector->Emit(opcode, output_count, outputs, input_count, inputs);
276 Emit(opcode | AddressingModeField::encode(kMode_MRI),
280 Emit(kMipsAdd | AddressingModeField::encode(kMode_None), addr_reg,
282 // Emit desired load opcode, using temp addr_reg.
283 Emit(opcode | AddressingModeField::encode(kMode_MRI),
330 Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
364 Emit(opcod
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/external/v8/src/compiler/mips64/
H A Dinstruction-selector-mips64.cc140 selector->Emit(opcode, g.DefineAsRegister(node),
148 selector->Emit(opcode, g.DefineAsRegister(node),
157 selector->Emit(opcode, g.DefineAsRegister(node),
237 selector->Emit(opcode, arraysize(outputs), outputs, arraysize(inputs),
312 selector->Emit(opcode, output_count, outputs, input_count, inputs);
340 selector->Emit(opcode | AddressingModeField::encode(kMode_MRI),
345 selector->Emit(kMips64Dadd | AddressingModeField::encode(kMode_None),
347 // Emit desired load opcode, using temp addr_reg.
348 selector->Emit(opcode | AddressingModeField::encode(kMode_MRI),
435 Emit(cod
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/external/llvm/include/llvm/Bitcode/
H A DBitstreamWriter.h115 void Emit(uint32_t Val, unsigned NumBits) { function in class:llvm::BitstreamWriter
136 Emit((uint32_t)Val, NumBits);
138 Emit((uint32_t)Val, 32);
139 Emit((uint32_t)(Val >> 32), NumBits-32);
155 // Emit the bits with VBR encoding, NumBits-1 bits at a time.
157 Emit((Val & ((1 << (NumBits-1))-1)) | (1 << (NumBits-1)), NumBits);
161 Emit(Val, NumBits);
171 // Emit the bits with VBR encoding, NumBits-1 bits at a time.
173 Emit(((uint32_t)Val & ((1 << (NumBits-1))-1)) |
178 Emit((uint32_
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/external/swiftshader/third_party/LLVM/include/llvm/Bitcode/
H A DBitstreamWriter.h90 void Emit(uint32_t Val, unsigned NumBits) { function in class:llvm::BitstreamWriter
115 Emit((uint32_t)Val, NumBits);
117 Emit((uint32_t)Val, 32);
118 Emit((uint32_t)(Val >> 32), NumBits-32);
137 // Emit the bits with VBR encoding, NumBits-1 bits at a time.
139 Emit((Val & ((1 << (NumBits-1))-1)) | (1 << (NumBits-1)), NumBits);
143 Emit(Val, NumBits);
152 // Emit the bits with VBR encoding, NumBits-1 bits at a time.
154 Emit(((uint32_t)Val & ((1 << (NumBits-1))-1)) |
159 Emit((uint32_
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/external/v8/src/asmjs/
H A Dasm-wasm-builder.cc112 foreign_init_function_->Emit(kExprEnd);
143 init_function_->Emit(kExprEnd); // finish init function.
263 builder_->current_function_builder_->Emit(kExprEnd);
281 current_function_builder_->Emit(kExprDrop);
294 if (scope_ == kFuncScope) current_function_builder_->Emit(kExprDrop);
312 current_function_builder_->Emit(kExprElse);
355 current_function_builder_->Emit(kExprReturn);
370 current_function_builder_->Emit(kExprI32LtS);
375 current_function_builder_->Emit(kExprElse);
380 current_function_builder_->Emit(kExprI32Gt
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/external/vixl/src/
H A Dcode-buffer-vixl.h114 void Emit8(uint8_t data) { Emit(data); }
116 void Emit16(uint16_t data) { Emit(data); }
118 void Emit32(uint32_t data) { Emit(data); }
120 void Emit64(uint64_t data) { Emit(data); }
127 void Emit(T value) { function in class:vixl::CodeBuffer
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86WinCOFFStreamer.cpp40 EHStreamer.Emit(*this);
/external/v8/src/compiler/ia32/
H A Dinstruction-selector-ia32.cc172 selector->Emit(opcode, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
179 selector->Emit(opcode, g.DefineAsRegister(node),
190 selector->Emit(avx_opcode, g.DefineAsRegister(node), operand0, operand1);
192 selector->Emit(sse_opcode, g.DefineSameAsFirst(node), operand0, operand1);
201 selector->Emit(avx_opcode, g.DefineAsRegister(node), g.Use(input));
203 selector->Emit(sse_opcode, g.DefineSameAsFirst(node), g.UseRegister(input));
253 Emit(code, 1, outputs, input_count, inputs);
305 Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
355 Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count,
416 Emit(opcod
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/external/v8/src/compiler/ppc/
H A Dinstruction-selector-ppc.cc77 selector->Emit(opcode, g.DefineAsRegister(node),
84 selector->Emit(opcode, g.DefineAsRegister(node),
92 selector->Emit(opcode, g.DefineAsRegister(node),
112 selector->Emit(opcode, output_count, outputs, 1, inputs);
160 selector->Emit(opcode, output_count, outputs, input_count, inputs);
162 selector->Emit(opcode, output_count, outputs, input_count, inputs);
227 Emit(opcode | AddressingModeField::encode(kMode_MRI),
230 Emit(opcode | AddressingModeField::encode(kMode_MRI),
233 Emit(opcode | AddressingModeField::encode(kMode_MRR),
293 Emit(cod
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/external/v8/src/compiler/arm/
H A Dinstruction-selector-arm.cc83 selector->Emit(opcode, g.DefineAsRegister(node),
89 selector->Emit(opcode, g.DefineAsRegister(node),
98 selector->Emit(
106 selector->Emit(opcode, g.DefineAsRegister(node),
113 selector->Emit(opcode, g.DefineAsRegister(node),
294 selector->Emit(opcode, output_count, outputs, input_count, inputs);
296 selector->Emit(opcode, output_count, outputs, input_count, inputs);
314 selector->Emit(div_opcode, result_operand, left_operand, right_operand);
320 selector->Emit(f64i32_opcode, left_double_operand, left_operand);
321 selector->Emit(f64i32_opcod
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/external/vixl/src/aarch64/
H A Dassembler-aarch64.cc182 Emit(BR | Rn(xn));
188 Emit(BLR | Rn(xn));
194 Emit(RET | Rn(xn));
198 void Assembler::b(int64_t imm26) { Emit(B | ImmUncondBranch(imm26)); }
202 Emit(B_cond | ImmCondBranch(imm19) | cond);
220 void Assembler::bl(int64_t imm26) { Emit(BL | ImmUncondBranch(imm26)); }
231 Emit(SF(rt) | CBZ | ImmCmpBranch(imm19) | Rt(rt));
243 Emit(SF(rt) | CBNZ | ImmCmpBranch(imm19) | Rt(rt));
261 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd));
353 Emit(TB
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/external/v8/src/compiler/arm64/
H A Dinstruction-selector-arm64.cc143 selector->Emit(opcode, g.DefineAsRegister(node),
150 selector->Emit(opcode, g.DefineAsRegister(node),
159 selector->Emit(opcode, g.DefineAsRegister(node),
229 selector->Emit(opcode, arraysize(outputs), outputs, arraysize(inputs),
480 selector->Emit(opcode, output_count, outputs, input_count, inputs);
482 selector->Emit(opcode, output_count, outputs, input_count, inputs);
503 selector->Emit(negate_opcode, g.DefineAsRegister(node),
558 selector->Emit(opcode, arraysize(outputs), outputs, input_count, inputs);
659 Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
720 Emit(opcod
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/external/v8/src/compiler/
H A Dinstruction-selector.h80 Instruction* Emit(InstructionCode opcode, InstructionOperand output,
82 Instruction* Emit(InstructionCode opcode, InstructionOperand output,
85 Instruction* Emit(InstructionCode opcode, InstructionOperand output,
88 Instruction* Emit(InstructionCode opcode, InstructionOperand output,
92 Instruction* Emit(InstructionCode opcode, InstructionOperand output,
96 Instruction* Emit(InstructionCode opcode, InstructionOperand output,
101 Instruction* Emit(InstructionCode opcode, InstructionOperand output,
106 Instruction* Emit(InstructionCode opcode, size_t output_count,
110 Instruction* Emit(Instruction* instr);
/external/v8/src/arm64/
H A Dassembler-arm64.cc388 void ConstPool::Emit(bool require_jump) { function in class:v8::internal::ConstPool
398 // Emit the constant pool. It is preceded by an optional branch if
416 // Emit branch if required
422 // Emit the header.
428 // Emit constant pool entries.
468 assm_->Emit(LDR_x_lit |
538 // Emit unique entries.
594 // Emit constant pool if necessary.
959 Emit(BLR | Rn(xzr));
979 Emit(B
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/external/v8/src/compiler/x64/
H A Dinstruction-selector-x64.cc288 Emit(code, 1, outputs, input_count, inputs);
336 Emit(code, 0, nullptr, input_count, inputs, temp_count, temps);
353 Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count,
376 Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count, inputs);
429 Emit(opcode, g.DefineAsRegister(node), g.UseRegister(buffer),
437 Emit(opcode, g.DefineAsRegister(node), g.UseRegister(buffer),
489 Emit(opcode, g.NoOutput(), g.UseRegister(buffer),
498 Emit(opcode, g.NoOutput(), g.UseRegister(buffer), g.UseRegister(offset),
559 selector->Emit(opcode, output_count, outputs, input_count, inputs);
576 Emit(kX64Movzxb
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/external/antlr/antlr-3.4/runtime/CSharp2/Sources/Antlr3.Runtime/Antlr.Runtime/
H A DLexer.cs127 Emit();
182 public virtual void Emit(IToken token) { method in class:Antlr.Runtime.Lexer
199 public virtual IToken Emit() { method in class:Antlr.Runtime.Lexer
204 Emit(t);
/external/antlr/antlr-3.4/runtime/CSharp3/Sources/Antlr3.Runtime/
H A DLexer.cs150 Emit();
222 public virtual void Emit( IToken token ) method in class:Antlr.Runtime.Lexer
240 public virtual IToken Emit() method in class:Antlr.Runtime.Lexer
246 Emit( t );

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