Searched refs:FP_TO_SINT (Results 1 - 25 of 46) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp153 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
155 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
157 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
171 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
173 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
175 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
188 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
190 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
192 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
194 { ISD::FP_TO_SINT, MV
[all...]
H A DARMISelLowering.cpp106 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
111 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
570 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
628 setTargetDAGCombine(ISD::FP_TO_SINT);
680 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
682 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
4177 if (Op.getOpcode() == ISD::FP_TO_SINT)
6736 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
6775 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6886 N0 = DAG.getNode(ISD::FP_TO_SINT, d
[all...]
/external/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp256 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 },
257 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
258 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
264 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
265 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 },
266 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 },
272 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
273 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 },
278 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
279 { ISD::FP_TO_SINT, MV
[all...]
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DISDOpcodes.h384 FP_TO_SINT, enumerator in enum:llvm::ISD::NodeType
/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h448 FP_TO_SINT, enumerator in enum:llvm::ISD::NodeType
/external/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h587 ISD::FP_TO_SINT, 0),
589 ISD::FP_TO_SINT, 0),
591 ISD::FP_TO_SINT, ISD::FP_TO_SINT),
593 ISD::FP_TO_SINT, 0),
595 ISD::FP_TO_SINT, 0),
597 ISD::FP_TO_SINT, ISD::FP_TO_SINT),
611 ISD::FP_TO_SINT, 0),
613 ISD::FP_TO_SINT,
[all...]
H A DX86TargetTransformInfo.cpp709 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
710 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 },
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp299 case ISD::FP_TO_SINT:
392 case ISD::FP_TO_SINT:
394 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
478 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
479 NewOpc = ISD::FP_TO_SINT;
H A DLegalizeFloatTypes.cpp759 case ISD::FP_TO_SINT:
887 bool Signed = N->getOpcode() == ISD::FP_TO_SINT;
1509 case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break;
1616 return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res);
1620 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
1641 DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32,
1648 DAG.getNode(ISD::FP_TO_SINT, dl,
1747 case ISD::FP_TO_SINT:
H A DLegalizeVectorTypes.cpp89 case ISD::FP_TO_SINT:
440 case ISD::FP_TO_SINT:
648 case ISD::FP_TO_SINT:
1484 case ISD::FP_TO_SINT:
2138 case ISD::FP_TO_SINT:
3097 case ISD::FP_TO_SINT:
H A DSelectionDAGDumper.cpp256 case ISD::FP_TO_SINT: return "fp_to_sint";
H A DLegalizeDAG.cpp2514 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2530 // so using FP_TO_SINT is valid
2531 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2532 OpToUse = ISD::FP_TO_SINT;
2536 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2932 case ISD::FP_TO_SINT:
2948 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2950 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
4050 case ISD::FP_TO_SINT:
4052 Node->getOpcode() == ISD::FP_TO_SINT, d
[all...]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp170 case ISD::FP_TO_SINT:
H A DLegalizeFloatTypes.cpp587 case ISD::FP_TO_SINT: Res = SoftenFloatOp_FP_TO_SINT(N); break;
734 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
1267 case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break;
1364 return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res);
1368 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
1388 DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32,
1394 DAG.getNode(ISD::FP_TO_SINT, dl,
H A DLegalizeVectorTypes.cpp83 case ISD::FP_TO_SINT:
460 case ISD::FP_TO_SINT:
985 case ISD::FP_TO_SINT:
1285 case ISD::FP_TO_SINT:
2037 case ISD::FP_TO_SINT:
H A DLegalizeDAG.cpp2689 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2705 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2706 OpToUse = ISD::FP_TO_SINT;
3151 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3152 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3869 case ISD::FP_TO_SINT:
3871 Node->getOpcode() == ISD::FP_TO_SINT, dl);
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
H A DSPUISelLowering.cpp325 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
327 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
331 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
333 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
335 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Expand);
383 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
386 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
2455 //! Lower ISD::FP_TO_SINT, ISD::FP_TO_UINT for i32
2470 (Op.getOpcode() == ISD::FP_TO_SINT)
2819 case ISD::FP_TO_SINT
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp259 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
260 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
370 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
388 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
394 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
515 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
646 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
701 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
751 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
6389 Op.getOpcode() == ISD::FP_TO_SINT
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
H A DAlphaISelLowering.cpp86 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
629 case ISD::FP_TO_SINT: {
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
H A DSparcISelLowering.cpp721 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1154 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
/external/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp125 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
196 setTargetDAGCombine(ISD::FP_TO_SINT);
841 // we can use FP_TO_SINT for uints too. The DAGLegalizer code for uint
843 case ISD::FP_TO_SINT: {
1969 case ISD::FP_TO_SINT: {
H A DAMDGPUISelLowering.cpp330 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
367 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
721 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1255 ISD::NodeType ToInt = Sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
2061 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
H A DPPCISelLowering.cpp176 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
177 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
3655 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4531 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4640 case ISD::FP_TO_SINT:
5231 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
5261 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
5264 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp2023 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
2024 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
2025 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
2038 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
2039 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1570 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1572 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
3042 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
3511 case ISD::FP_TO_SINT:
3517 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)

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