Searched refs:FSQRT (Results 1 - 25 of 52) sorted by relevance

123

/external/one-true-awk/
H A Dawk.h116 #define FSQRT 2 macro
H A Dlex.c82 { "sqrt", FSQRT, BLTIN },
H A Drun.c1499 case FSQRT:
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DISDOpcodes.h446 // FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
450 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator in enum:llvm::ISD::NodeType
/external/valgrind/none/tests/ppc32/
H A Dround.c33 FMSUB, FNMADD, FNMSUB, FSQRT enumerator in enum:__anon29720
926 for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2)
1034 case FSQRT:
1139 case FSQRT:
1208 for (op = FADD; op <= FSQRT; op++) {
/external/valgrind/none/tests/ppc64/
H A Dround.c33 FMSUB, FNMADD, FNMSUB, FSQRT enumerator in enum:__anon29769
926 for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2)
1034 case FSQRT:
1139 case FSQRT:
1208 for (op = FADD; op <= FSQRT; op++) {
/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h520 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
524 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator in enum:llvm::ISD::NodeType
H A DBasicTTIImpl.h201 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT);
742 ISDs.push_back(ISD::FSQRT);
/external/llvm/lib/Target/PowerPC/
H A DPPCCTRLoops.cpp301 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
344 Opcode = ISD::FSQRT; break;
H A DPPCISelLowering.cpp192 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
197 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
463 setOperationAction(ISD::FSQRT, VT, Expand);
534 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
590 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
817 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
820 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
823 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
826 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
884 setTargetDAGCombine(ISD::FSQRT);
[all...]
/external/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h265 X86_INTRINSIC_DATA(avx_sqrt_pd_256, INTR_TYPE_1OP, ISD::FSQRT, 0),
266 X86_INTRINSIC_DATA(avx_sqrt_ps_256, INTR_TYPE_1OP, ISD::FSQRT, 0),
1429 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1430 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1431 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_512, INTR_TYPE_1OP_MASK_RM, ISD::FSQRT,
1433 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1434 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0),
1435 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_512, INTR_TYPE_1OP_MASK_RM, ISD::FSQRT,
1873 X86_INTRINSIC_DATA(sse_sqrt_ps, INTR_TYPE_1OP, ISD::FSQRT, 0),
1923 X86_INTRINSIC_DATA(sse2_sqrt_pd, INTR_TYPE_1OP, ISD::FSQRT,
[all...]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp174 case ISD::FSQRT:
H A DLegalizeFloatTypes.cpp90 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break;
870 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break;
H A DLegalizeVectorTypes.cpp87 case ISD::FSQRT:
464 case ISD::FSQRT:
1311 case ISD::FSQRT:
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
H A DAlphaISelLowering.cpp120 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
121 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp158 case ISD::FSQRT: return "fsqrt";
H A DLegalizeVectorOps.cpp308 case ISD::FSQRT:
H A DLegalizeFloatTypes.cpp103 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break;
1040 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break;
1883 case ISD::FSQRT:
H A DLegalizeVectorTypes.cpp94 case ISD::FSQRT:
653 case ISD::FSQRT:
2167 case ISD::FSQRT:
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/
H A DMBlazeDisassembler.cpp235 case 0x380: return MBlaze::FSQRT;
/external/v8/src/arm64/
H A Ddisasm-arm64.cc1001 FORMAT(FSQRT, "fsqrt");
H A Dconstants-arm64.h1071 FSQRT = FSQRT_s, enumerator in enum:v8::internal::FPDataProcessing1SourceOp
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1747 setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1772 setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1824 setOperationAction(ISD::FSQRT, MVT::f32, Promote);
3071 case ISD::FSQRT: return LowerF128Op(Op, DAG,
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
H A DSPUISelLowering.cpp221 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
222 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
/external/v8/src/ppc/
H A Dconstants-ppc.h1845 V(fsqrt, FSQRT, 0xFC00002C) \

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