/external/one-true-awk/ |
H A D | awk.h | 116 #define FSQRT 2 macro
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H A D | lex.c | 82 { "sqrt", FSQRT, BLTIN },
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H A D | run.c | 1499 case FSQRT:
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 446 // FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 450 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator in enum:llvm::ISD::NodeType
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/external/valgrind/none/tests/ppc32/ |
H A D | round.c | 33 FMSUB, FNMADD, FNMSUB, FSQRT enumerator in enum:__anon29720 926 for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2) 1034 case FSQRT: 1139 case FSQRT: 1208 for (op = FADD; op <= FSQRT; op++) {
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/external/valgrind/none/tests/ppc64/ |
H A D | round.c | 33 FMSUB, FNMADD, FNMSUB, FSQRT enumerator in enum:__anon29769 926 for (s = (op != FSQRT ? -1 : 1); s < 2; s += 2) 1034 case FSQRT: 1139 case FSQRT: 1208 for (op = FADD; op <= FSQRT; op++) {
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 520 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 524 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator in enum:llvm::ISD::NodeType
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H A D | BasicTTIImpl.h | 201 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); 742 ISDs.push_back(ISD::FSQRT);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCCTRLoops.cpp | 301 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break; 344 Opcode = ISD::FSQRT; break;
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H A D | PPCISelLowering.cpp | 192 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 197 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 463 setOperationAction(ISD::FSQRT, VT, Expand); 534 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 590 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 817 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 820 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 823 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand); 826 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); 884 setTargetDAGCombine(ISD::FSQRT); [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86IntrinsicsInfo.h | 265 X86_INTRINSIC_DATA(avx_sqrt_pd_256, INTR_TYPE_1OP, ISD::FSQRT, 0), 266 X86_INTRINSIC_DATA(avx_sqrt_ps_256, INTR_TYPE_1OP, ISD::FSQRT, 0), 1429 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0), 1430 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0), 1431 X86_INTRINSIC_DATA(avx512_mask_sqrt_pd_512, INTR_TYPE_1OP_MASK_RM, ISD::FSQRT, 1433 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_128, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0), 1434 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_256, INTR_TYPE_1OP_MASK, ISD::FSQRT, 0), 1435 X86_INTRINSIC_DATA(avx512_mask_sqrt_ps_512, INTR_TYPE_1OP_MASK_RM, ISD::FSQRT, 1873 X86_INTRINSIC_DATA(sse_sqrt_ps, INTR_TYPE_1OP, ISD::FSQRT, 0), 1923 X86_INTRINSIC_DATA(sse2_sqrt_pd, INTR_TYPE_1OP, ISD::FSQRT, [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 174 case ISD::FSQRT:
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H A D | LegalizeFloatTypes.cpp | 90 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; 870 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break;
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H A D | LegalizeVectorTypes.cpp | 87 case ISD::FSQRT: 464 case ISD::FSQRT: 1311 case ISD::FSQRT:
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
H A D | AlphaISelLowering.cpp | 120 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 121 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 158 case ISD::FSQRT: return "fsqrt";
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H A D | LegalizeVectorOps.cpp | 308 case ISD::FSQRT:
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H A D | LegalizeFloatTypes.cpp | 103 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; 1040 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break; 1883 case ISD::FSQRT:
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H A D | LegalizeVectorTypes.cpp | 94 case ISD::FSQRT: 653 case ISD::FSQRT: 2167 case ISD::FSQRT:
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
H A D | MBlazeDisassembler.cpp | 235 case 0x380: return MBlaze::FSQRT;
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/external/v8/src/arm64/ |
H A D | disasm-arm64.cc | 1001 FORMAT(FSQRT, "fsqrt");
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H A D | constants-arm64.h | 1071 FSQRT = FSQRT_s, enumerator in enum:v8::internal::FPDataProcessing1SourceOp
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1747 setOperationAction(ISD::FSQRT, MVT::f128, Legal); 1772 setOperationAction(ISD::FSQRT, MVT::f128, Custom); 1824 setOperationAction(ISD::FSQRT, MVT::f32, Promote); 3071 case ISD::FSQRT: return LowerF128Op(Op, DAG,
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 221 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 222 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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/external/v8/src/ppc/ |
H A D | constants-ppc.h | 1845 V(fsqrt, FSQRT, 0xFC00002C) \
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