Searched refs:IsWrite (Results 1 - 15 of 15) sorted by relevance

/external/compiler-rt/lib/esan/
H A Dworking_set.h28 bool IsWrite);
H A Desan.h45 void processRangeAccess(uptr PC, uptr Addr, int Size, bool IsWrite);
H A Desan.cpp65 void processRangeAccess(uptr PC, uptr Addr, int Size, bool IsWrite) { argument
67 IsWrite ? 'w' : 'r', Addr, Size);
72 processRangeAccessWorkingSet(PC, Addr, Size, IsWrite);
H A Dworking_set.cpp82 bool IsWrite) {
81 processRangeAccessWorkingSet(uptr PC, uptr Addr, SIZE_T Size, bool IsWrite) argument
/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmInstrumentation.cpp211 bool IsWrite,
215 bool IsWrite,
222 void InstrumentMemOperand(X86Operand &Op, unsigned AccessSize, bool IsWrite,
280 X86Operand &Op, unsigned AccessSize, bool IsWrite,
287 InstrumentMemOperandSmall(Op, AccessSize, IsWrite, RegCtx, Ctx, Out);
289 InstrumentMemOperandLarge(Op, AccessSize, IsWrite, RegCtx, Ctx, Out);
313 InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, RegCtx, Ctx,
323 InstrumentMemOperand(*Op, AccessSize, false /* IsWrite */, RegCtx, Ctx,
332 InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, RegCtx, Ctx, Out);
341 InstrumentMemOperand(*Op, AccessSize, true /* IsWrite */, RegCt
279 InstrumentMemOperand( X86Operand &Op, unsigned AccessSize, bool IsWrite, const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) argument
412 const bool IsWrite = MII.get(Inst.getOpcode()).mayStore(); local
595 EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx, MCStreamer &Out, const RegisterContext &RegCtx) argument
616 InstrumentMemOperandSmall( X86Operand &Op, unsigned AccessSize, bool IsWrite, const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) argument
691 InstrumentMemOperandLarge( X86Operand &Op, unsigned AccessSize, bool IsWrite, const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) argument
864 EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx, MCStreamer &Out, const RegisterContext &RegCtx) argument
887 InstrumentMemOperandSmall( X86Operand &Op, unsigned AccessSize, bool IsWrite, const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) argument
963 InstrumentMemOperandLarge( X86Operand &Op, unsigned AccessSize, bool IsWrite, const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) argument
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/external/compiler-rt/lib/tsan/tests/unit/
H A Dtsan_shadow_test.cc28 EXPECT_EQ(s.IsWrite(), true);
/external/llvm/lib/Transforms/Instrumentation/
H A DAddressSanitizer.cpp479 /// and set IsWrite/Alignment. Otherwise return nullptr.
480 Value *isInterestingMemoryAccess(Instruction *I, bool *IsWrite,
486 Value *Addr, uint32_t TypeSize, bool IsWrite,
489 uint32_t TypeSize, bool IsWrite,
495 bool IsWrite, size_t AccessSizeIndex,
936 /// and set IsWrite/Alignment. Otherwise return nullptr.
938 bool *IsWrite,
948 *IsWrite = false;
954 *IsWrite = true;
960 *IsWrite
937 isInterestingMemoryAccess(Instruction *I, bool *IsWrite, uint64_t *TypeSize, unsigned *Alignment) argument
1031 bool IsWrite = false; local
1087 generateCrashCode(Instruction *InsertBefore, Value *Addr, bool IsWrite, size_t AccessSizeIndex, Value *SizeArgument, uint32_t Exp) argument
1136 instrumentAddress(Instruction *OrigIns, Instruction *InsertBefore, Value *Addr, uint32_t TypeSize, bool IsWrite, Value *SizeArgument, bool UseCalls, uint32_t Exp) argument
1198 instrumentUnusualSizeOrAlignment( Instruction *I, Value *Addr, uint32_t TypeSize, bool IsWrite, Value *SizeArgument, bool UseCalls, uint32_t Exp) argument
1797 bool IsWrite; local
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H A DThreadSanitizer.cpp461 bool IsWrite = isa<StoreInst>(*I); local
462 Value *Addr = IsWrite
468 if (IsWrite && isVtableAccess(I)) {
486 if (!IsWrite && isVtableAccess(I)) {
492 const unsigned Alignment = IsWrite
499 OnAccessFunc = IsWrite ? TsanWrite[Idx] : TsanRead[Idx];
501 OnAccessFunc = IsWrite ? TsanUnalignedWrite[Idx] : TsanUnalignedRead[Idx];
503 if (IsWrite) NumInstrumentedWrites++;
/external/llvm/lib/Analysis/
H A DLoopAccessAnalysis.cpp609 bool IsWrite = Accesses.count(MemAccessInfo(Ptr, true)); local
610 MemAccessInfo Access(Ptr, IsWrite);
612 if (IsWrite)
634 RtCheck.insert(TheLoop, Ptr, IsWrite, DepId, ASId, StridesMap, PSE);
749 bool IsWrite = AC.getInt(); local
753 bool IsReadOnlyPtr = ReadOnlyPtr.count(Ptr) && !IsWrite;
758 assert(((IsReadOnlyPtr && UseDeferred) || IsWrite ||
762 MemAccessInfo Access(Ptr, IsWrite);
769 // "a[b[i]] +="). Hence, we need the second check for "!IsWrite".
779 if ((IsWrite || IsReadOnlyPt
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/external/compiler-rt/lib/tsan/rtl/
H A Dtsan_rtl.h200 DCHECK_EQ(kAccessIsWrite, IsWrite());
250 bool ALWAYS_INLINE IsWrite() const { return !IsRead(); } function in class:__tsan::Shadow
279 DCHECK_EQ(v, (!IsWrite() && !kIsWrite) || (IsAtomic() && kIsAtomic));
287 (IsAtomic() == kIsAtomic && !IsWrite() <= !kIsWrite));
295 (IsAtomic() == kIsAtomic && !IsWrite() >= !kIsWrite));
H A Dtsan_rtl_report.cc171 mop->write = s.IsWrite();
/external/pdfium/third_party/lcms/src/
H A Dcmsio0.c1074 NewIcc -> IsWrite = TRUE;
1102 NewIcc -> IsWrite = TRUE;
1136 NewIcc -> IsWrite = TRUE;
1461 if (Icc ->IsWrite) {
1463 Icc ->IsWrite = FALSE; // Assure no further writting
H A Dlcms2_internal.h751 cmsBool IsWrite; member in struct:_cms_iccprofile_struct
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3402 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
3403 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1864 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); local
1880 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit

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