Searched refs:OP_INSBF (Results 1 - 11 of 11) sorted by relevance
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| H A D | nv50_ir_target_gm107.cpp | 90 if (insn->op == OP_INSBF || insn->op == OP_EXTBF)
209 case OP_INSBF:
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| H A D | nv50_ir_target_nv50.cpp | 437 case OP_INSBF:
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| H A D | nv50_ir_lowering_nvc0.cpp | 762 bld.mkOp3(OP_INSBF, TYPE_U32, hnd, rHnd, bld.mkImm(0x1400), sHnd);
847 bld.mkOp3(OP_INSBF, TYPE_U32, src, ticRel, bld.mkImm(0x0917), src);
849 bld.mkOp3(OP_INSBF, TYPE_U32, src, tscRel, bld.mkImm(0x0710), src);
883 bld.mkOp3(OP_INSBF, TYPE_U32,
910 bld.mkOp3(OP_INSBF, TYPE_U32, i->getSrc(s),
2319 ptr = bld.mkOp3v(OP_INSBF, TYPE_U32, bld.getSSA(),
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| H A D | nv50_ir.h | 148 OP_INSBF, // insert first src1[8:15] bits of src0 into src2 at src1[0:7] enumerator in enum:nv50_ir::operation
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| H A D | nv50_ir_target_nvc0.cpp | 136 { OP_INSBF, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
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| H A D | nv50_ir_from_tgsi.cpp | 2915 offset = mkOp3v(OP_INSBF, TYPE_U32, getScratch(),
3383 mkOp3(OP_INSBF, TYPE_U32, dst0[c], val1, mkImm(0x1010), val0);
3662 mkOp3(OP_INSBF, TYPE_U32, val0, src2, mkImm(0x808), src1);
3674 mkOp3(OP_INSBF, TYPE_U32, val0, src3, mkImm(0x808), src2);
3675 mkOp3(OP_INSBF, TYPE_U32, dst0[c], src1, val0, src0);
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| H A D | nv50_ir_emit_gk110.cpp | 2572 case OP_INSBF:
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| H A D | nv50_ir_emit_nv50.cpp | 2054 case OP_INSBF:
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| H A D | nv50_ir_emit_gm107.cpp | 3179 case OP_INSBF:
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| H A D | nv50_ir_emit_nvc0.cpp | 2791 case OP_INSBF:
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| H A D | nv50_ir_peephole.cpp | 746 case OP_INSBF: {
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