Searched refs:ORR (Results 1 - 25 of 41) sorted by relevance

12

/external/libxaac/decoder/armv8/
H A Dixheaacd_calcmaxspectralline.s43 ORR V3.16B, V0.16B, V3.16B
44 ORR V3.16B, V1.16B, V3.16B
53 ORR W4, W4, W1
55 ORR W4, W4, W2
56 ORR W4, W4, W3
65 ORR W4, W4, W2
/external/arm-neon-tests/
H A DInitCache.s19 ORR r0, r0, #(0x1 <<12) ; enable I Cache
21 ORR r0, r0, #(0x1 <<2) ; enable D Cache
23 ORR r0, r0, #0x1 ; enable MMU
31 ORR r0, r0, #2 ; L2EN bit, enable L2 cache
33 ;ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI
34 ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI
35 ORR r0, r0, #(0x1 << 5) ;Enables caching NEON data within the L1 data cache
43 ORR r0, r0, #(0x1 <<11) ; Enable all forms of branch prediction
/external/libxaac/decoder/armv7/
H A Dixheaacd_calcmaxspectralline.s54 ORR R4, R4, R1
56 ORR R4, R4, R2
59 ORR R4, R4, R3
66 ORR R4, R4, R2
H A Dixheaacd_complex_fft_p2.s28 ORR r4, r7, r6, LSL #2
31 ORR r4, r7, r6, LSL #4
35 ORR r4, r7, r6, LSL #8
188 ORR r4, r3, r4, LSL#1
191 ORR r6, r3, r6, LSL#1
194 ORR r5, r3, r5, LSL#1
197 ORR r7, r3, r7, LSL#1
206 ORR r4, r3, r4, LSL#1
209 ORR r8, r3, r8, LSL#1
212 ORR r
[all...]
H A Dixheaacd_complex_ifft_p2.s28 ORR r4, r7, r6, LSL #2
31 ORR r4, r7, r6, LSL #4
35 ORR r4, r7, r6, LSL #8
188 ORR r4, r3, r4, LSL#1
191 ORR r6, r3, r6, LSL#1
194 ORR r5, r3, r5, LSL#1
197 ORR r7, r3, r7, LSL#1
206 ORR r4, r3, r4, LSL#1
209 ORR r8, r3, r8, LSL#1
212 ORR r
[all...]
H A Dixheaacd_expsubbandsamples.s59 ORR r12, r12, r1
86 ORR r12, r12, r3
89 ORR r12, r12, r3
H A Dixheaacd_mps_complex_fft_64_asm.s176 ORR r4, r3, r4, LSL#1
179 ORR r6, r3, r6, LSL#1
182 ORR r5, r3, r5, LSL#1
185 ORR r7, r3, r7, LSL#1
194 ORR r4, r3, r4, LSL#1
197 ORR r8, r3, r8, LSL#1
200 ORR r5, r3, r5, LSL#1
203 ORR r9, r3, r9, LSL#1
212 ORR r4, r3, r4, LSL#1
215 ORR r1
[all...]
H A Dixheaacd_auto_corr.s111 ORR r5, r6, r5
113 ORR r5, r6, r5
115 ORR r5, r9, r5
116 ORR r5, r14, r5
H A Dixheaacd_enery_calc_per_subband.s85 ORR R6, R6, R4
H A Dixheaacd_decorr_filter2.s752 ORR r8, r8, #0x07f00
/external/boringssl/src/ssl/test/runner/poly1305/
H A Dsum_arm.s36 ORR R3<<6, R9, R9
37 ORR R4<<12, g, g
38 ORR R5<<18, R11, R11
114 ORR R1<<6, g, g
115 ORR R2<<12, R11, R11
116 ORR R3<<18, R12, R12
124 ORR R3, R4, R4
171 ORR R11<<6, R12, R12
172 ORR R5<<6, R14, R14
181 ORR R
[all...]
/external/libhevc/common/arm64/
H A Dihevc_sao_band_offset_luma.s152 ORR v4.8b, v4.8b , v25.8b //band_table.val[3] = vorr_u8(band_table.val[3], au1_cmp)
160 ORR v3.8b, v3.8b , v24.8b //band_table.val[2] = vorr_u8(band_table.val[2], au1_cmp)
170 ORR v2.8b, v2.8b , v23.8b //band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
180 ORR v1.8b, v1.8b , v22.8b //band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
H A Dihevc_sao_band_offset_chroma.s176 ORR v4.8b, v4.8b , v13.8b //band_table.val[3] = vorr_u8(band_table.val[3], au1_cmp)
184 ORR v3.8b, v3.8b , v14.8b //band_table.val[2] = vorr_u8(band_table.val[2], au1_cmp)
194 ORR v2.8b, v2.8b , v15.8b //band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
203 ORR v1.8b, v1.8b , v16.8b //band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
250 ORR v12.8b, v12.8b , v17.8b //band_table.val[3] = vorr_u8(band_table.val[3], au1_cmp)
258 ORR v11.8b, v11.8b , v18.8b //band_table.val[2] = vorr_u8(band_table.val[2], au1_cmp)
268 ORR v10.8b, v10.8b , v19.8b //band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
278 ORR v9.8b, v9.8b , v20.8b //band_table.val[0] = vorr_u8(band_table.val[0], au1_cmp)
/external/pcre/dist2/src/sljit/
H A DsljitNativeARM_64.c103 #define ORR 0xaa000000 macro
450 /* A large amount of number can be constructed from ORR and MOVx,
669 return push_inst(compiler, ORR | RD(dst) | RN(TMP_ZERO) | RM(arg2));
695 return push_inst(compiler, (ORR ^ (1 << 31)) | RD(dst) | RN(TMP_ZERO) | RM(arg2));
742 FAIL_IF(push_inst(compiler, (ORR ^ inv_bits) | RD(dst) | RN(arg1) | RM(arg2)));
980 return push_inst(compiler, ORR | RD(arg) | RN(TMP_ZERO) | RM(TMP_LR));
1142 FAIL_IF(push_inst(compiler, ORR | RD(SLJIT_S0) | RN(TMP_ZERO) | RM(SLJIT_R0)));
1144 FAIL_IF(push_inst(compiler, ORR | RD(SLJIT_S1) | RN(TMP_ZERO) | RM(SLJIT_R1)));
1146 FAIL_IF(push_inst(compiler, ORR | RD(SLJIT_S2) | RN(TMP_ZERO) | RM(SLJIT_R2)));
1261 FAIL_IF(push_inst(compiler, ORR | R
[all...]
/external/v8/src/arm64/
H A Dconstants-arm64.h499 ORR = 0x20000000, enumerator in enum:v8::internal::LogicalOp
500 ORN = ORR | NOT,
514 ORR_w_imm = LogicalImmediateFixed | ORR,
515 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits,
533 ORR_w = LogicalShiftedFixed | ORR,
534 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits,
H A Dmacro-assembler-arm64.cc92 case ORR: // Fall through.
108 case ORR:
431 LogicalImmediate(dst, AppropriateZeroRegFor(dst), n, imm_s, imm_r, ORR);
H A Dmacro-assembler-arm64-inl.h94 LogicalMacro(rd, rn, operand, ORR);
/external/llvm/test/MC/AArch64/
H A Darm64-aliases.s25 ; ORR Rd, Rn, Rn is a MOV
195 ; ORR is mostly repeating bit sequences and cannot encode -1, so it only
/external/vixl/src/aarch64/
H A Dconstants-aarch64.h539 ORR = 0x20000000, enumerator in enum:vixl::aarch64::LogicalOp
540 ORN = ORR | NOT,
554 ORR_w_imm = LogicalImmediateFixed | ORR,
555 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits,
573 ORR_w = LogicalShiftedFixed | ORR,
574 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits,
H A Dmacro-assembler-aarch64.cc537 ORR);
772 LogicalMacro(rd, rn, operand, ORR);
837 case ORR:
855 case ORR:
/external/v8/src/arm/
H A Dconstants-arm.h153 ORR = 12 << 21, // Logical (inclusive) OR. enumerator in enum:v8::internal::Opcode
/external/tremolo/Tremolo/
H A DbitwiseARM.s108 ORR r10,r10,r12,LSL r5 @ r10= first r5+8 bits
304 ORR r10,r10,r12,LSL r5 @ r10= first r5+8 bits
H A Ddpen.s146 ORR r0, r14,r10,LSL #8 @ r7 = chase = (next<<8) | r14
206 ORR r0, r14,r10,LSL #16 @ r7 = chase = (next<<16) | r14
/external/llvm/test/MC/ARM/
H A Dbasic-thumb-instructions.s448 @ ORR
/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dbasic-thumb-instructions.s397 @ ORR

Completed in 502 milliseconds

12