Searched refs:RegisterRef (Results 1 - 19 of 19) sorted by relevance

/external/llvm/lib/Target/Hexagon/
H A DHexagonRDF.h21 bool covers(RegisterRef RA, RegisterRef RR) const override;
22 bool covers(const RegisterSet &RRs, RegisterRef RR) const override;
H A DRDFLiveness.h34 typedef std::map<RegisterRef,NodeSet> RefMap;
40 NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr<RefNode*> RefA,
43 NodeSet getAllReachingDefsRec(RegisterRef RefRR, NodeAddr<RefNode*> RefA,
45 NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr<DefNode*> DefA,
82 // map: NodeId -> (map: RegisterRef -> NodeSet)
100 RegisterRef RR) const;
101 RegisterRef getRestrictedRegRef(NodeAddr<RefNode*> RA) const;
102 unsigned getPhysReg(RegisterRef RR) const;
H A DHexagonRDF.cpp19 bool HexagonRegisterAliasInfo::covers(RegisterRef RA, RegisterRef RB) const {
37 bool HexagonRegisterAliasInfo::covers(const RegisterSet &RRs, RegisterRef RR)
H A DRDFCopy.h32 typedef std::map<RegisterRef, RegisterRef> EqualityMap;
42 std::map<RegisterRef,std::map<NodeId,NodeId>> RDefMap;
H A DRDFCopy.cpp35 RegisterRef DstR = { Dst.getReg(), Dst.getSubReg() };
36 RegisterRef SrcR = { Src.getReg(), Src.getSubReg() };
59 RegisterRef DefR = { Dst.getReg(), Dst.getSubReg() };
66 RegisterRef DR = { DefR.Reg, S };
67 RegisterRef SR = { I.Reg, I.SubReg };
152 dbgs() << ' ' << Print<RegisterRef>(J.first, DFG) << '='
153 << Print<RegisterRef>(J.second, DFG);
158 dbgs() << Print<RegisterRef>(R.first, DFG) << " -> {";
183 RegisterRef DR = DA.Addr->getRegRef();
187 RegisterRef S
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H A DHexagonBitTracker.h22 typedef BitTracker::RegisterRef RegisterRef; typedef in struct:llvm::HexagonEvaluator
H A DHexagonExpandCondsets.cpp215 struct RegisterRef { struct in class:__anon14329::HexagonExpandCondsets
216 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()), function in struct:__anon14329::HexagonExpandCondsets::RegisterRef
218 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {} function in struct:__anon14329::HexagonExpandCondsets::RegisterRef
219 bool operator== (RegisterRef RR) const {
222 bool operator!= (RegisterRef RR) const { return !operator==(RR); }
223 bool operator< (RegisterRef RR) const {
236 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
237 bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec);
257 MachineInstr *getReachingDefForPred(RegisterRef RD,
265 void renameInRange(RegisterRef R
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H A DBitTracker.h31 struct RegisterRef;
48 RegisterCell get(RegisterRef RR) const;
49 void put(RegisterRef RR, const RegisterCell &RC);
50 void subst(RegisterRef OldRR, RegisterRef NewRR);
91 struct BitTracker::RegisterRef { struct in class:llvm::BitTracker
92 RegisterRef(unsigned R = 0, unsigned S = 0) function in struct:llvm::BitTracker::RegisterRef
94 RegisterRef(const MachineOperand &MO) function in struct:llvm::BitTracker::RegisterRef
347 uint16_t getRegBitWidth(const RegisterRef &RR) const;
349 RegisterCell getCell(const RegisterRef
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H A DRDFGraph.h369 struct RegisterRef { struct
373 RegisterRef() = default;
374 RegisterRef(const RegisterRef &RR) = default;
375 RegisterRef &operator= (const RegisterRef &RR) = default;
376 bool operator== (const RegisterRef &RR) const {
379 bool operator!= (const RegisterRef &RR) const {
382 bool operator< (const RegisterRef &RR) const {
386 typedef std::set<RegisterRef> RegisterSe
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H A DHexagonBitSimplify.cpp167 static bool getSubregMask(const BitTracker::RegisterRef &RR,
174 BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH);
182 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI);
183 static bool isTransparentCopy(const BitTracker::RegisterRef &RD,
184 const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI);
363 bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR,
390 BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH) {
850 const BitTracker::RegisterRef
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H A DHexagonBlockRanges.h35 struct RegisterRef { struct in struct:llvm::HexagonBlockRanges
37 bool operator<(RegisterRef R) const {
41 typedef std::set<RegisterRef> RegisterSet;
136 typedef std::map<RegisterRef,RangeList> RegToRangeMap;
139 static RegisterSet expandToSubRegs(RegisterRef R,
H A DRDFLiveness.cpp45 OS << ' ' << Print<RegisterRef>(I.first, P.G) << '{';
87 NodeList Liveness::getAllReachingDefs(RegisterRef RefRR,
111 RegisterRef RR = TA.Addr->getRegRef();
240 NodeSet Liveness::getAllReachingDefsRec(RegisterRef RefRR,
281 NodeSet Liveness::getAllReachedUses(RegisterRef RefRR,
515 RegisterRef RR = NodeAddr<DefNode*>(Ds[0]).Addr->getRegRef();
516 dbgs() << '<' << Print<RegisterRef>(RR, DFG) << '>';
604 RegisterRef RR = R.first;
642 dbgs() << ' ' << Print<RegisterRef>({unsigned(x),0}, DFG);
733 RegisterRef R
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H A DRDFGraph.cpp32 raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterRef> &P) {
90 << Print<RegisterRef>(RA.Addr->getRegRef(), G) << '>';
283 OS << ' ' << Print<RegisterRef>(I, P.G);
293 << '<' << Print<RegisterRef>(I->Addr->getRegRef(), P.G) << '>';
379 RegisterRef RefNode::getRegRef() const {
389 void RefNode::setRegRef(RegisterRef RR) {
573 bool RegisterAliasInfo::covers(RegisterRef RA, RegisterRef RB) const {
593 bool RegisterAliasInfo::covers(const RegisterSet &RRs, RegisterRef RR) const {
617 std::vector<RegisterRef> RegisterAliasInf
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H A DBitTracker.cpp314 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const {
340 BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR,
368 void BT::MachineEvaluator::putCell(const RegisterRef &RR, RegisterCell RC,
742 RegisterRef RD = MI.getOperand(0);
744 RegisterRef RS = MI.getOperand(1);
746 RegisterRef RT = MI.getOperand(3);
761 RegisterRef RD = MI.getOperand(0);
762 RegisterRef RS = MI.getOperand(1);
792 RegisterRef DefRR(MD);
812 RegisterRef R
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H A DHexagonBlockRanges.cpp254 RegisterRef R, const MachineRegisterInfo &MRI,
285 std::map<RegisterRef,IndexType> LastDef, LastUse;
297 auto closeRange = [&LastUse,&LastDef,&LiveMap] (RegisterRef R) -> void {
315 RegisterRef R = { Op.getReg(), Op.getSubReg() };
329 RegisterRef R = { Op.getReg(), Op.getSubReg() };
382 auto addDeadRanges = [&IndexMap,&LiveMap,&DeadMap] (RegisterRef R) -> void {
H A DHexagonBitTracker.cpp84 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
102 std::vector<BT::RegisterRef> Vector;
109 Vector[i] = BT::RegisterRef(MO);
116 const BT::RegisterRef &operator[](unsigned n) const {
918 RegisterRef PR = BI.getOperand(0);
1073 RegisterRef RD = MD;
1102 RegisterRef RD = MI.getOperand(0);
1103 RegisterRef RS = MI.getOperand(1);
H A DHexagonRDFOpt.cpp98 auto mapRegs = [MI,&EM] (RegisterRef DstR, RegisterRef SrcR) -> void {
H A DHexagonOptAddrMode.cpp73 std::map<RegisterRef, std::map<NodeId, NodeId>> RDefMap;
148 RegisterRef OffsetRR;
151 RegisterRef RR = UA.Addr->getRegRef();
194 RegisterRef UR = UN.Addr->getRegRef();
218 RegisterRef DR = DA.Addr->getRegRef();
H A DHexagonFrameLowering.cpp1885 auto getRegClass = [&MRI,&HRI] (HexagonBlockRanges::RegisterRef R)
2110 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(),
2171 HexagonBlockRanges::RegisterRef FoundRR = { FoundR, 0 };

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