Searched refs:SLW (Results 1 - 8 of 8) sorted by relevance
/external/pcre/dist2/src/sljit/ |
H A D | sljitNativePPC_32.c | 220 return push_inst(compiler, SLW | RC(flags) | S(src1) | A(dst) | B(src2));
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H A D | sljitNativePPC_64.c | 353 return push_inst(compiler, ((flags & ALT_FORM2) ? SLW : SLD) | RC(flags) | S(src1) | A(dst) | B(src2));
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H A D | sljitNativePPC_common.c | 204 #define SLW (HI(31) | LO(24)) macro
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 4805 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 4813 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 5137 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 5139 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 5148 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 1582 MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
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H A D | PPCISelDAGToDAG.cpp | 3967 // SLW and SRW always clear the higher-order bits. 3968 if (Op32.getMachineOpcode() == PPC::SLW || 4181 case PPC::SLW: NewOpcode = PPC::SLW8; break;
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H A D | PPCISelLowering.cpp | 8596 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg) 8604 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) 9321 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg) 9323 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg) 9332 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
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/external/capstone/arch/PowerPC/ |
H A D | PPCGenAsmWriter.inc | 834 23090U, // SLW 2107 0U, // SLW
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