Searched refs:SLW (Results 1 - 8 of 8) sorted by relevance

/external/pcre/dist2/src/sljit/
H A DsljitNativePPC_32.c220 return push_inst(compiler, SLW | RC(flags) | S(src1) | A(dst) | B(src2));
H A DsljitNativePPC_64.c353 return push_inst(compiler, ((flags & ALT_FORM2) ? SLW : SLD) | RC(flags) | S(src1) | A(dst) | B(src2));
H A DsljitNativePPC_common.c204 #define SLW (HI(31) | LO(24)) macro
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4805 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4813 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5137 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
5139 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
5148 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1582 MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
H A DPPCISelDAGToDAG.cpp3967 // SLW and SRW always clear the higher-order bits.
3968 if (Op32.getMachineOpcode() == PPC::SLW ||
4181 case PPC::SLW: NewOpcode = PPC::SLW8; break;
H A DPPCISelLowering.cpp8596 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
8604 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
9321 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
9323 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
9332 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
/external/capstone/arch/PowerPC/
H A DPPCGenAsmWriter.inc834 23090U, // SLW
2107 0U, // SLW

Completed in 358 milliseconds