| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 45 SXTB, enumerator in enum:llvm::AArch64_AM::ShiftExtendType
64 case AArch64_AM::SXTB: return "sxtb";
131 case 4: return AArch64_AM::SXTB;
158 case AArch64_AM::SXTB: return 4; break;
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 364 SXTB, enumerator in enum:llvm::AArch64SE::ShiftExtSpecifiers
|
| /external/vixl/test/aarch64/ |
| H A D | test-api-aarch64.cc | 312 VIXL_CHECK(!Operand(w12, SXTB).IsPlainRegister());
|
| H A D | test-assembler-aarch64.cc | 382 __ Add(sp, sp, Operand(x17, SXTB));
429 __ Mvn(x11, Operand(x2, SXTB, 1));
604 __ Mov(x24, Operand(x13, SXTB, 1));
658 __ Mov(w20, Operand(w11, SXTB, 1));
742 __ Orr(w10, w0, Operand(w1, SXTB));
836 __ Orn(w10, w0, Operand(w1, SXTB));
903 __ And(w10, w0, Operand(w1, SXTB));
1041 __ Bic(w10, w0, Operand(w1, SXTB));
1165 __ Eor(w10, w0, Operand(w1, SXTB));
1232 __ Eon(w10, w0, Operand(w1, SXTB));
[all...] |
| H A D | test-disasm-aarch64.cc | 435 COMPARE(adds(w15, w16, Operand(w17, SXTB, 4)), "adds w15, w16, w17, sxtb #4");
436 COMPARE(add(x18, x19, Operand(x20, SXTB, 3)), "add x18, x19, w20, sxtb #3");
461 COMPARE(subs(w15, w16, Operand(w17, SXTB, 4)), "subs w15, w16, w17, sxtb #4");
462 COMPARE(sub(x18, x19, Operand(x20, SXTB, 3)), "sub x18, x19, w20, sxtb #3");
466 COMPARE(cmp(w0, Operand(w1, SXTB, 1)), "cmp w0, w1, sxtb #1");
2409 COMPARE_MACRO(Csel(x12, Operand(x13, LSL, 13), Operand(x14, SXTB), eq),
2415 Operand(x14, SXTB),
|
| /external/llvm/test/MC/ARM/ |
| H A D | basic-thumb-instructions.s | 638 @ SXTB/SXTH
|
| H A D | basic-thumb2-instructions.s | 3129 @ SXTB
3187 @ SXTB
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| H A D | basic-thumb-instructions.s | 587 @ SXTB/SXTH
|
| H A D | basic-thumb2-instructions.s | 2632 @ SXTB
2690 @ SXTB
|
| H A D | basic-arm-instructions.s | 2191 @ SXTB
|
| /external/pcre/dist2/src/sljit/ |
| H A D | sljitNativeARM_T2_32.c | 159 #define SXTB 0xb240 macro
701 return push_inst16(compiler, SXTB | RD3(dst) | RN3(arg2));
|
| H A D | sljitNativeARM_32.c | 121 #define SXTB 0xe6af0070 macro
1014 return push_inst(compiler, (op == SLJIT_MOV_U8 ? UXTB : SXTB) | RD(dst) | RM(src2));
|
| /external/v8/src/compiler/arm64/ |
| H A D | code-generator-arm64.cc | 119 return Operand(InputRegister32(index), SXTB);
149 return Operand(InputRegister64(index), SXTB);
|
| /external/v8/src/arm64/ |
| H A D | constants-arm64.h | 343 SXTB = 4, enumerator in enum:v8::internal::Extend
|
| H A D | assembler-arm64.cc | 2503 case SXTB:
|
| H A D | simulator-arm64.cc | 986 case SXTB:
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2641 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 },
2886 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 },
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2038 Opc = isThumb ? ARM::t2SXTB : ARM::SXTB;
|
| /external/vixl/src/aarch64/ |
| H A D | constants-aarch64.h | 290 SXTB = 4, enumerator in enum:vixl::aarch64::Extend
|
| H A D | simulator-aarch64.cc | 397 case SXTB:
|
| H A D | assembler-aarch64.cc | 4197 case SXTB:
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 988 return (ET == AArch64_AM::UXTB || ET == AArch64_AM::SXTB ||
2393 .Case("sxtb", AArch64_AM::SXTB)
|
| /external/capstone/arch/ARM/ |
| H A D | ARMGenAsmWriter.inc | 480 26169U, // SXTB
3273 2560U, // SXTB
7640 // SXTB, SXTB16, SXTH, UXTB, UXTB16, UXTH, t2SXTB, t2SXTB16, t2SXTH, t2UX...
9173 // (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 1094 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB;
|
| H A D | AArch64ISelDAGToDAG.cpp | 377 return AArch64_AM::SXTB;
|