| /external/vixl/test/aarch32/ |
| H A D | test-disasm-a32.cc | 1538 COMPARE_BOTH(Sbc(r0, r1, -5), "adc r0, r1, #4\n");
1563 COMPARE_BOTH(Sbc(r0, r0, 0xabcd),
1567 COMPARE_BOTH(Sbc(r0, r0, -0xabcd),
1571 COMPARE_BOTH(Sbc(r0, r0, 0x1234abcd),
1576 COMPARE_BOTH(Sbc(r0, r0, -0x1234abcd),
3561 COMPARE_T32(Sbc(eq, r0, r0, r1),
3565 COMPARE_T32(Sbc(eq, r0, r1, r2),
4178 CHECK_T32_16(Sbc(DontCare, r7, r7, r6), "sbcs r7, r6\n");
4180 CHECK_T32_16_IT_BLOCK(Sbc(DontCare, eq, r7, r7, r6),
|
| H A D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 132 M(Sbc) \
|
| H A D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 132 M(Sbc) \
|
| H A D | test-simulator-cond-rd-rn-operand-const-a32.cc | 132 M(Sbc) \
|
| H A D | test-simulator-cond-rd-rn-operand-const-t32.cc | 132 M(Sbc) \
|
| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 132 M(Sbc) \
|
| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 132 M(Sbc) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 132 M(Sbc) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 132 M(Sbc) \
|
| H A D | test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 132 M(Sbc) \
|
| /external/v8/src/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 251 void MacroAssembler::Sbc(const Register& rd, function in class:v8::internal::MacroAssembler
274 Sbc(rd, zr, operand);
|
| H A D | macro-assembler-arm64.h | 237 inline void Sbc(const Register& rd,
|
| /external/swiftshader/third_party/subzero/src/ |
| H A D | IceInstARM32.h | 416 Sbc, enumerator in enum:Ice::ARM32::InstARM32::InstKindARM32
1015 using InstARM32Sbc = InstARM32ThreeAddrGPR<InstARM32::Sbc>;
|
| H A D | IceInstARM32.cpp | 3495 template class InstARM32ThreeAddrGPR<InstARM32::Sbc>;
|
| /external/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.cc | 1742 void MacroAssembler::Sbc(const Register& rd, function in class:vixl::aarch64::MacroAssembler
1761 Sbc(rd, zr, operand);
|
| H A D | macro-assembler-aarch64.h | 687 void Sbc(const Register& rd, const Register& rn, const Operand& operand);
|
| /external/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 3344 void Sbc(Condition cond, Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::MacroAssembler
3358 void Sbc(Register rd, Register rn, const Operand& operand) { function in class:vixl::aarch32::MacroAssembler
3359 Sbc(al, rd, rn, operand);
3361 void Sbc(FlagsUpdate flags, function in class:vixl::aarch32::MacroAssembler
3368 Sbc(cond, rd, rn, operand);
3380 Sbc(cond, rd, rn, operand);
3385 void Sbc(FlagsUpdate flags, function in class:vixl::aarch32::MacroAssembler
3389 Sbc(flags, al, rd, rn, operand);
|
| /external/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 8706 __ Sbc(x7, x4, Operand(x3, LSR, 4));
8712 __ Sbc(w12, w4, Operand(w3, LSR, 4));
8721 __ Sbc(x20, x4, Operand(x3, LSR, 4));
8727 __ Sbc(w25, w4, Operand(w3, LSR, 4));
8775 __ Sbc(x12, x1, Operand(w2, UXTW, 4));
8787 __ Sbc(x22, x1, Operand(w2, UXTW, 4));
8866 __ Sbc(x9, x0, Operand(0x1234567890abcdef));
8867 __ Sbc(w10, w0, Operand(0xffffffff));
8876 __ Sbc(x20, x0, Operand(0x1234567890abcdef));
8877 __ Sbc(w2
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