| /external/v8/src/compiler/arm64/ |
| H A D | code-generator-arm64.cc | 1029 __ Udiv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
1032 __ Udiv(i.OutputRegister32(), i.InputRegister32(0), i.InputRegister32(1));
1052 __ Udiv(temp, i.InputRegister(0), i.InputRegister(1));
1059 __ Udiv(temp, i.InputRegister32(0), i.InputRegister32(1));
|
| /external/swiftshader/third_party/subzero/src/ |
| H A D | IceInstARM32.h | 424 Udiv, enumerator in enum:Ice::ARM32::InstARM32::InstKindARM32
1018 using InstARM32Udiv = InstARM32ThreeAddrGPR<InstARM32::Udiv>;
|
| H A D | IceTargetLoweringARM32.cpp | 467 case InstArithmetic::Udiv:
485 case InstArithmetic::Udiv:
517 case InstArithmetic::Udiv:
2916 case InstArithmetic::Udiv:
3128 case InstArithmetic::Udiv: {
3503 case InstArithmetic::Udiv:
5658 case InstArithmetic::Udiv:
5667 NewShiftKind = ArithInst->getOp() == InstArithmetic::Udiv
|
| H A D | IceConverter.cpp | 283 return convertArithInstruction(Instr, Ice::InstArithmetic::Udiv);
|
| H A D | IceTargetLoweringX86BaseImpl.h | 1960 case InstArithmetic::Udiv:
2064 case InstArithmetic::Udiv:
2187 case InstArithmetic::Udiv:
2314 case InstArithmetic::Udiv: {
7361 case InstArithmetic::Udiv:
7393 case InstArithmetic::Udiv:
|
| H A D | IceTargetLoweringMIPS32.cpp | 374 case InstArithmetic::Udiv:
2741 case InstArithmetic::Udiv:
2929 case InstArithmetic::Udiv: {
|
| H A D | WasmTranslator.cpp | 442 Control()->appendInst(InstArithmetic::create(Func, InstArithmetic::Udiv,
|
| H A D | IceInstARM32.cpp | 3498 template class InstARM32ThreeAddrGPR<InstARM32::Udiv>;
|
| H A D | PNaClTranslator.cpp | 1784 Op = Ice::InstArithmetic::Udiv;
|
| /external/v8/src/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 1193 void MacroAssembler::Udiv(const Register& rd, function in class:v8::internal::MacroAssembler
|
| H A D | macro-assembler-arm64.h | 558 inline void Udiv(const Register& rd, const Register& rn, const Register& rm);
|
| /external/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 1651 __ Udiv(w0, w16, w16);
1652 __ Udiv(w1, w17, w16);
1657 __ Udiv(x5, x16, x16);
1658 __ Udiv(x6, x17, x18);
1663 __ Udiv(w10, w19, w21);
1665 __ Udiv(x12, x19, x21);
1667 __ Udiv(x14, x20, x21);
1670 __ Udiv(w22, w19, w17);
1672 __ Udiv(x24, x20, x18);
1675 __ Udiv(x2
[all...] |
| /external/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 2076 void Udiv(const Register& rd, const Register& rn, const Register& rm) { function in class:vixl::aarch64::MacroAssembler
|
| /external/vixl/test/aarch32/ |
| H A D | test-simulator-cond-rd-rn-rm-a32.cc | 143 M(Udiv) \
|
| H A D | test-simulator-cond-rd-rn-rm-t32.cc | 142 M(Udiv) \
|
| /external/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 4822 void Udiv(Condition cond, Register rd, Register rn, Register rm) { function in class:vixl::aarch32::MacroAssembler
4832 void Udiv(Register rd, Register rn, Register rm) { Udiv(al, rd, rn, rm); } function in class:vixl::aarch32::MacroAssembler
|
| /external/swiftshader/src/Reactor/ |
| H A D | SubzeroReactor.cpp | 740 return createArithmetic(Ice::InstArithmetic::Udiv, lhs, rhs);
|