| /external/libxaac/decoder/armv7/ |
| H A D | ixheaacd_pre_twiddle_compute.s | 175 VSHL.S32 Q10, Q10, Q7
179 VSHL.S32 Q11, Q11, Q7
182 VSHL.S32 Q9, Q15, Q7
183 VSHL.S32 Q8, Q14, Q7
241 VSHL.S32 Q10, Q10, Q7
242 VSHL.S32 Q11, Q11, Q7
245 VSHL.S32 Q9, Q15, Q7
248 VSHL.S32 Q8, Q14, Q7
296 VSHL.S32 Q10, Q10, Q7
297 VSHL
[all...] |
| H A D | ixheaacd_imdct_using_fft.s | 395 VSHL.S32 q12, q12, #3
397 VSHL.S32 q5, q5, #3
399 VSHL.S32 q9, q9, #3
401 VSHL.S32 q2, q2, #3
403 VSHL.S32 q0, q0, #3
405 VSHL.S32 q7, q7, #3
407 VSHL.S32 q14, q14, #3
409 VSHL.S32 q4, q4, #3
411 VSHL.S32 q13, q13, #3
413 VSHL
[all...] |
| H A D | ixheaacd_sbr_imdct_using_fft.s | 400 VSHL.S32 q12, q12, #1
402 VSHL.S32 q5, q5, #1
404 VSHL.S32 q9, q9, #1
406 VSHL.S32 q2, q2, #1
408 VSHL.S32 q0, q0, #1
410 VSHL.S32 q7, q7, #1
412 VSHL.S32 q14, q14, #1
414 VSHL.S32 q4, q4, #1
416 VSHL.S32 q13, q13, #1
418 VSHL
[all...] |
| H A D | ixheaacd_dec_DCT2_64_asm.s | 80 VSHL.S32 D0, D0, #1
121 VSHL.S32 Q15, Q15, #1
123 VSHL.S32 Q14, Q14, #1
176 VSHL.S32 Q15, Q15, #1
179 VSHL.S32 Q14, Q14, #1
223 VSHL.S32 Q15, Q15, #1
226 VSHL.S32 Q14, Q14, #1
273 VSHL.S32 Q15, Q15, #1
274 VSHL.S32 Q14, Q14, #1
319 VSHL
[all...] |
| H A D | ixheaacd_fft32x32_ld.s | 404 VSHL.S32 q12, q12, #3 @ch
406 VSHL.S32 q5, q5, #3 @ch
408 VSHL.S32 q9, q9, #3 @ch
410 VSHL.S32 q2, q2, #3 @ch
412 VSHL.S32 q0, q0, #3 @ch
414 VSHL.S32 q7, q7, #3 @ch
416 VSHL.S32 q14, q14, #3 @ch
418 VSHL.S32 q4, q4, #3 @ch
420 VSHL.S32 q13, q13, #3 @ch
422 VSHL
[all...] |
| H A D | ixheaacd_sbr_qmfsyn64_winadd.s | 47 VSHL.S32 Q10, Q15, Q14
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86IntrinsicsInfo.h | 298 X86_INTRINSIC_DATA(avx2_psll_d, INTR_TYPE_2OP, X86ISD::VSHL, 0),
299 X86_INTRINSIC_DATA(avx2_psll_q, INTR_TYPE_2OP, X86ISD::VSHL, 0),
300 X86_INTRINSIC_DATA(avx2_psll_w, INTR_TYPE_2OP, X86ISD::VSHL, 0),
1242 X86_INTRINSIC_DATA(avx512_mask_psll_d, INTR_TYPE_2OP_MASK, X86ISD::VSHL, 0),
1243 X86_INTRINSIC_DATA(avx512_mask_psll_d_128, INTR_TYPE_2OP_MASK, X86ISD::VSHL, 0),
1244 X86_INTRINSIC_DATA(avx512_mask_psll_d_256, INTR_TYPE_2OP_MASK, X86ISD::VSHL, 0),
1248 X86_INTRINSIC_DATA(avx512_mask_psll_q, INTR_TYPE_2OP_MASK, X86ISD::VSHL, 0),
1249 X86_INTRINSIC_DATA(avx512_mask_psll_q_128, INTR_TYPE_2OP_MASK, X86ISD::VSHL, 0),
1250 X86_INTRINSIC_DATA(avx512_mask_psll_q_256, INTR_TYPE_2OP_MASK, X86ISD::VSHL, 0),
1254 X86_INTRINSIC_DATA(avx512_mask_psll_w_128, INTR_TYPE_2OP_MASK, X86ISD::VSHL,
[all...] |
| H A D | X86ISelLowering.h | 311 VSHL, VSRL, VSRA,
|
| H A D | X86ISelLowering.cpp | 17127 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
19934 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
20199 Opc = X86ISD::VSHL;
22187 case X86ISD::VSHL: return "X86ISD::VSHL";
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 110 VSHL, // ...left enumerator in enum:llvm::ARMISD::NodeType
|
| H A D | ARMISelLowering.cpp | 879 case ARMISD::VSHL: return "ARMISD::VSHL";
3102 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3110 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3365 // Lower vector shifts on NEON to use VSHL.
7575 VShiftOpc = ARMISD::VSHL;
7720 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.h | 113 VSHL,
|
| H A D | AArch64ISelLowering.cpp | 887 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
5898 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5901 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
6639 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0),
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 109 VSHL, // ...left
|
| H A D | ARMISelLowering.cpp | 1183 case ARMISD::VSHL: return "ARMISD::VSHL";
4260 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4268 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4805 // Lower vector shifts on NEON to use VSHL.
10584 VShiftOpc = ARMISD::VSHL;
10727 return DAG.getNode(ARMISD::VSHL, dl, VT, N->getOperand(0),
11212 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHL))
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| H A D | X86ISelLowering.h | 223 // VSHL, VSRL - Vector logical left / right shift.
224 VSHL, VSRL, enumerator in enum:llvm::X86ISD::NodeType
|
| H A D | X86ISelLowering.cpp | 4888 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
10685 case X86ISD::VSHL: return "X86ISD::VSHL";
|
| H A D | X86GenDAGISel.inc | [all...] |
| /external/v8/src/arm/ |
| H A D | assembler-arm.cc | 4449 enum NeonShiftOp { VSHL, VSHR }; enumerator in enum:v8::internal::NeonShiftOp
4461 if (op == VSHL) {
4480 emit(EncodeNeonShiftOp(VSHL, dt, dst, src, shift));
|
| /external/valgrind/none/tests/arm/ |
| H A D | neon128.stdout.exp | 429 ---- VSHL (register) ----
2544 ---- VSHL (immediate) ----
|
| H A D | neon64.stdout.exp | 618 ---- VSHL (register) ----
3824 ---- VSHL (immediate) ----
|