| /external/google-breakpad/src/processor/ |
| H A D | contained_range_map_unittest.cc | 57 ContainedRangeMap<unsigned int, int> crm; local
61 ASSERT_TRUE (crm.StoreRange(10, 10, 1));
62 ASSERT_FALSE(crm.StoreRange(10, 10, 2)); // exactly equal to 1
63 ASSERT_FALSE(crm.StoreRange(11, 10, 3)); // begins inside 1 and extends up
64 ASSERT_FALSE(crm.StoreRange( 9, 10, 4)); // begins below 1 and ends inside
65 ASSERT_TRUE (crm.StoreRange(11, 9, 5)); // contained by existing
66 ASSERT_TRUE (crm.StoreRange(12, 7, 6));
67 ASSERT_TRUE (crm.StoreRange( 9, 12, 7)); // contains existing
68 ASSERT_TRUE (crm.StoreRange( 9, 13, 8));
69 ASSERT_TRUE (crm
[all...] |
| /external/kernel-headers/original/uapi/asm-arm/asm/ |
| H A D | kvm.h | 142 #define __ARM_CP15_REG(op1,crn,crm,op2) \
146 ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
151 #define __ARM_CP15_REG64(op1,crm) \
152 (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
|
| /external/kernel-headers/original/uapi/asm-arm64/asm/ |
| H A D | kvm.h | 189 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
194 ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
|
| /external/v8/src/arm/ |
| H A D | assembler-arm.h | 1058 CRegister crd, CRegister crn, CRegister crm,
1062 CRegister crd, CRegister crn, CRegister crm,
1066 Register rd, CRegister crn, CRegister crm,
1070 Register rd, CRegister crn, CRegister crm,
1074 Register rd, CRegister crn, CRegister crm,
1078 Register rd, CRegister crn, CRegister crm,
|
| H A D | assembler-arm.cc | 2315 CRegister crm,
2320 crd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | crm.code());
2324 CRegister crn, CRegister crm, int opcode_2) {
2325 cdp(coproc, opcode_1, crd, crn, crm, opcode_2, kSpecialCondition);
2333 CRegister crm,
2338 rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm.code());
2342 CRegister crn, CRegister crm, int opcode_2) {
2343 mcr(coproc, opcode_1, rd, crn, crm, opcode_2, kSpecialCondition);
2351 CRegister crm,
2356 rd.code()*B12 | coproc*B8 | (opcode_2 & 7)*B5 | B4 | crm
2311 cdp(Coprocessor coproc, int opcode_1, CRegister crd, CRegister crn, CRegister crm, int opcode_2, Condition cond) argument
2323 cdp2(Coprocessor coproc, int opcode_1, CRegister crd, CRegister crn, CRegister crm, int opcode_2) argument
2329 mcr(Coprocessor coproc, int opcode_1, Register rd, CRegister crn, CRegister crm, int opcode_2, Condition cond) argument
2341 mcr2(Coprocessor coproc, int opcode_1, Register rd, CRegister crn, CRegister crm, int opcode_2) argument
2347 mrc(Coprocessor coproc, int opcode_1, Register rd, CRegister crn, CRegister crm, int opcode_2, Condition cond) argument
2359 mrc2(Coprocessor coproc, int opcode_1, Register rd, CRegister crn, CRegister crm, int opcode_2) argument
[all...] |
| H A D | simulator-arm.cc | 3600 int crm = instr->Bits(3, 0); local
3606 if (((crm == 10) && (opc2 == 5)) || // CP15DMB
3607 ((crm == 10) && (opc2 == 4)) || // CP15DSB
3608 ((crm == 5) && (opc2 == 4))) { // CP15ISB
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 1515 uint64_t crm = fieldFromInstruction(insn, 8, 4); local
1520 pstate_field == AArch64PState::UAO) && crm > 1)
1524 Inst.addOperand(MCOperand::createImm(crm));
|
| /external/capstone/arch/AArch64/ |
| H A D | AArch64Disassembler.c | 1621 uint64_t crm = fieldFromInstruction(insn, 8, 4); local
1626 MCOperand_CreateImm0(Inst, crm);
|
| /external/vixl/src/aarch64/ |
| H A D | constants-aarch64.h | 342 template<int op0, int op1, int crn, int crm, int op2>
349 (crm << CRm_offset) |
|
| H A D | macro-assembler-aarch64.h | 1689 void Sys(int op1, int crn, int crm, int op2, const Register& rt = xzr) { argument
1692 sys(op1, crn, crm, op2, rt);
|
| H A D | assembler-aarch64.cc | 1414 void Assembler::sys(int op1, int crn, int crm, int op2, const Register& xt) { argument
1416 Emit(SYS | ImmSysOp1(op1) | CRn(crn) | CRm(crm) | ImmSysOp2(op2) | Rt(xt));
|
| H A D | assembler-aarch64.h | 1241 void sys(int op1, int crn, int crm, int op2, const Register& xt = xzr);
1243 // System instruction with pre-encoded op (op1:crn:crm:op2).
|