| /external/libhevc/common/arm64/ |
| H A D | ihevc_deblk_luma_horz.s | 137 csneg x9,x9,x9,pl
142 csneg x8,x8,x8,pl // dp0 value is stored in x8
166 csneg x12,x12,x12,pl
172 csneg x11,x11,x11,pl // dp3 value is stored in x8
228 csneg x2,x2,x2,pl
231 csneg x8,x8,x8,pl
240 csneg x7,x7,x7,pl
284 csneg x8,x8,x8,pl
288 csneg x2,x2,x2,pl
298 csneg x
[all...] |
| H A D | ihevc_deblk_luma_vert.s | 130 csneg x9,x9,x9,pl
140 csneg x8,x8,x8,pl
165 csneg x12,x12,x12,pl
171 csneg x11,x11,x11,pl // dp3 value is stored in x8
226 csneg x8,x8,x8,pl
229 csneg x2,x2,x2,pl
239 csneg x7,x7,x7,pl
279 csneg x8,x8,x8,pl
283 csneg x2,x2,x2,pl
292 csneg x
[all...] |
| /external/llvm/test/MC/AArch64/ |
| H A D | basic-a64-instructions.s | 1383 csneg w1, w0, w19, ne
1384 csneg wzr, w5, w9, eq
1385 csneg w9, wzr, w30, gt
1386 csneg w1, w28, wzr, mi
1387 // CHECK: csneg w1, w0, w19, ne // encoding: [0x01,0x14,0x93,0x5a]
1388 // CHECK: csneg wzr, w5, w9, eq // encoding: [0xbf,0x04,0x89,0x5a]
1389 // CHECK: csneg w9, wzr, w30, gt // encoding: [0xe9,0xc7,0x9e,0x5a]
1390 // CHECK: csneg w1, w28, wzr, mi // encoding: [0x81,0x47,0x9f,0x5a]
1392 csneg x19, x23, x29, lt
1393 csneg xz
[all...] |
| H A D | arm64-arithmetic-encoding.s | 556 csneg w1, w2, w3, eq
557 csneg x1, x2, x3, eq
|
| H A D | basic-a64-diagnostics.s | 1375 csneg w20, w21, wsp, mi
1376 csneg x0, sp, x29, le
1378 // CHECK-ERROR-NEXT: csneg w20, w21, wsp, mi
1381 // CHECK-ERROR-NEXT: csneg x0, sp, x29, le
|
| /external/valgrind/none/tests/arm64/ |
| H A D | integer.stdout.exp | 875 cmp x17,x18 ; csneg x16,x17,x18,eq :: rd 8593c2e5aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV
876 cmp x17,x18 ; csneg x16,x17,x18,ne :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV
877 cmp x17,x18 ; csneg x16,x17,x18,cc :: rd 8593c2e5aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV
878 cmp x17,x18 ; csneg x16,x17,x18,cs :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV
879 cmp x17,x18 ; csneg x16,x17,x18,mi :: rd 8593c2e5aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV
880 cmp x17,x18 ; csneg x16,x17,x18,pl :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV
881 cmp x17,x18 ; csneg x16,x17,x18,vc :: rd 8593c2e5aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV
882 cmp x17,x18 ; csneg x16,x17,x18,vs :: rd afa6ef803bc9291c rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 30000000 CV
908 cmp w17,w18 ; csneg w16,w17,w18,eq :: rd 00000000aedb9b6b rm afa6ef803bc9291c, rn 7a6c3d1a51246495, cin 0, nzcv 80000000 N
909 cmp w17,w18 ; csneg w1
[all...] |
| /external/capstone/suite/MC/AArch64/ |
| H A D | basic-a64-instructions.s.cs | 524 0x01,0x14,0x93,0x5a = csneg w1, w0, w19, ne
525 0xbf,0x04,0x89,0x5a = csneg wzr, w5, w9, eq
526 0xe9,0xc7,0x9e,0x5a = csneg w9, wzr, w30, gt
527 0x81,0x47,0x9f,0x5a = csneg w1, w28, wzr, mi
528 0xf3,0xb6,0x9d,0xda = csneg x19, x23, x29, lt
529 0x7f,0xa4,0x84,0xda = csneg xzr, x3, x4, ge
530 0xe5,0x27,0x86,0xda = csneg x5, xzr, x6, hs
531 0x07,0x35,0x9f,0xda = csneg x7, x8, xzr, lo
548 0xa3,0xd4,0x85,0x5a = csneg w3, w5, w5, le
549 0x9f,0xc4,0x84,0x5a = csneg wz
[all...] |
| /external/v8/src/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 526 csneg(rd, rn, rm, cond);
|
| H A D | assembler-arm64.cc | 1353 void Assembler::csneg(const Register& rd, function in class:v8::internal::Assembler
1389 csneg(rd, rn, rn, NegateCondition(cond));
|
| H A D | assembler-arm64.h | 1254 void csneg(const Register& rd,
|
| /external/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 136 __ csneg(w7, w8, w9, hi);
137 __ csneg(w7, w8, w9, ls);
138 __ csneg(x10, x11, x12, eq);
139 __ csneg(x10, x11, x12, ne);
|
| H A D | test-disasm-aarch64.cc | 2163 COMPARE(csneg(w18, w19, w20, vs), "csneg w18, w19, w20, vs");
2164 COMPARE(csneg(x21, x22, x23, vc), "csneg x21, x22, x23, vc");
2182 COMPARE(csneg(x6, x7, x8, al), "csneg x6, x7, x8, al");
2183 COMPARE(csneg(x7, x8, x9, nv), "csneg x7, x8, x9, nv");
|
| /external/vixl/src/aarch64/ |
| H A D | assembler-aarch64.cc | 660 void Assembler::csneg(const Register& rd, function in class:vixl::aarch64::Assembler
696 csneg(rd, rn, rn, InvertCondition(cond));
|
| H A D | assembler-aarch64.h | 836 void csneg(const Register& rd,
|
| H A D | macro-assembler-aarch64.h | 1158 csneg(rd, rn, rm, cond);
|