Searched refs:fcvtn (Results 1 - 13 of 13) sorted by relevance

/external/llvm/test/MC/AArch64/
H A Dneon-simd-misc.s425 fcvtn v13.4h, v21.4s
426 fcvtn v4.2s, v0.2d
430 // CHECK: fcvtn v13.4h, v21.4s // encoding: [0xad,0x6a,0x21,0x0e]
431 // CHECK: fcvtn v4.2s, v0.2d // encoding: [0x04,0x68,0x61,0x0e]
H A Darm64-advsimd.s862 fcvtn v2.4h, v4.4s
863 fcvtn v3.2s, v5.2d
869 ; CHECK: fcvtn v2.4h, v4.4s ; encoding: [0x82,0x68,0x21,0x0e]
870 ; CHECK: fcvtn v3.2s, v5.2d ; encoding: [0xa3,0x68,0x61,0x0e]
H A Dneon-diagnostics.s5798 fcvtn v2.8h, v4.4s
5799 fcvtn v6.4s, v8.2d
5804 // CHECK-ERROR: fcvtn v2.8h, v4.4s
5807 // CHECK-ERROR: fcvtn v6.4s, v8.2d
/external/capstone/suite/MC/AArch64/
H A Dneon-simd-misc.s.cs136 0xad,0x6a,0x21,0x0e = fcvtn v13.4h, v21.4s
137 0x04,0x68,0x61,0x0e = fcvtn v4.2s, v0.2d
/external/vixl/src/aarch64/
H A Dassembler-aarch64.h1433 void fcvtn(const VRegister& vd, const VRegister& vn);
H A Dmacro-assembler-aarch64.h1241 fcvtn(vd, vn);
H A Dsimulator-aarch64.h2923 LogicVRegister fcvtn(VectorFormat vform,
H A Dsimulator-aarch64.cc3115 fcvtn(vf_fcvtn, rd, rn);
H A Dassembler-aarch64.cc2315 void Assembler::fcvtn(const VRegister& vd, const VRegister& vn) {
H A Dlogic-aarch64.cc4540 LogicVRegister Simulator::fcvtn(VectorFormat vform, function in class:vixl::aarch64::Simulator
/external/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc2579 __ fcvtn(v11.V2S(), v1.V2D());
2580 __ fcvtn(v8.V4H(), v2.V4S());
H A Dtest-simulator-aarch64.cc4314 DEFINE_TEST_NEON_2DIFF_FP_NARROW(fcvtn, Conversions)
/external/valgrind/none/tests/arm64/
H A Dfp_and_simd.stdout.exp26688 fcvtn v22.4h, v23.4s 3e80398f54c6346f38686a10aa85e392 a0d83ef4380b82357abee438e0a3a204 00000000000000008000022e7c00fc00 a0d83ef4380b82357abee438e0a3a204 fpsr=00000000
26690 fcvtn v22.2s, v23.2d 8779cc5b2a997db3d694043bcd86849b 0ab84637730d826f0b5ee27312980014 00000000000000000000000000000000 0ab84637730d826f0b5ee27312980014 fpsr=00000000
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