Searched refs:fcvtn2 (Results 1 - 12 of 12) sorted by relevance

/external/llvm/test/MC/AArch64/
H A Dneon-simd-misc.s423 fcvtn2 v2.8h, v4.4s
424 fcvtn2 v6.4s, v8.2d
428 // CHECK: fcvtn2 v2.8h, v4.4s // encoding: [0x82,0x68,0x21,0x4e]
429 // CHECK: fcvtn2 v6.4s, v8.2d // encoding: [0x06,0x69,0x61,0x4e]
H A Darm64-advsimd.s864 fcvtn2 v4.8h, v6.4s
865 fcvtn2 v5.4s, v7.2d
871 ; CHECK: fcvtn2 v4.8h, v6.4s ; encoding: [0xc4,0x68,0x21,0x4e]
872 ; CHECK: fcvtn2 v5.4s, v7.2d ; encoding: [0xe5,0x68,0x61,0x4e]
H A Dneon-diagnostics.s5800 fcvtn2 v13.4h, v21.4s
5801 fcvtn2 v4.2s, v0.2d
5810 // CHECK-ERROR: fcvtn2 v13.4h, v21.4s
5813 // CHECK-ERROR: fcvtn2 v4.2s, v0.2d
/external/capstone/suite/MC/AArch64/
H A Dneon-simd-misc.s.cs134 0x82,0x68,0x21,0x4e = fcvtn2 v2.8h, v4.4s
135 0x06,0x69,0x61,0x4e = fcvtn2 v6.4s, v8.2d
/external/vixl/src/aarch64/
H A Dassembler-aarch64.h1436 void fcvtn2(const VRegister& vd, const VRegister& vn);
H A Dmacro-assembler-aarch64.h1246 fcvtn2(vd, vn);
H A Dsimulator-aarch64.h2926 LogicVRegister fcvtn2(VectorFormat vform,
H A Dsimulator-aarch64.cc3113 fcvtn2(vf_fcvtn, rd, rn);
H A Dassembler-aarch64.cc2322 void Assembler::fcvtn2(const VRegister& vd, const VRegister& vn) {
H A Dlogic-aarch64.cc4557 LogicVRegister Simulator::fcvtn2(VectorFormat vform, function in class:vixl::aarch64::Simulator
/external/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc2581 __ fcvtn2(v24.V4S(), v29.V2D());
2582 __ fcvtn2(v4.V8H(), v10.V4S());
/external/valgrind/none/tests/arm64/
H A Dfp_and_simd.stdout.exp26689 fcvtn2 v22.8h, v23.4s b02f71346d7a88047007203680cef2a0 4b1e8a60f1a03d7f7d941bc7634e4c91 7c00fc007c007c007007203680cef2a0 4b1e8a60f1a03d7f7d941bc7634e4c91 fpsr=00000000
26691 fcvtn2 v22.4s, v23.2d 959001d77486fe17d17262ee15ec2759 ba56f08c97ebfcff786513dc15d436c7 92b784657f800000d17262ee15ec2759 ba56f08c97ebfcff786513dc15d436c7 fpsr=00000000
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