Searched refs:lanes (Results 1 - 25 of 32) sorted by relevance

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/external/gemmlowp/meta/generators/
H A Dzip_Nx8_neon.py28 """Prepares read lanes for the zip operation.
33 zip_lanes: number of lanes to prepare.
40 lanes = []
44 lanes.append(ZipLane(input_address, registers.DoubleRegister(),
48 lanes.append(ZipLane(address_register, registers.DoubleRegister(),
52 return lanes
64 def GenerateClearAggregators(emitter, lanes):
65 for lane in lanes:
69 def GenerateLoadAggregateStore(emitter, lanes, output_address, alignment):
70 """Emit inner loop code for reading N lanes an
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H A Dqnt_Nx8_neon.py26 def BuildName(lanes, leftovers, aligned):
27 name = 'qnt_%dx8' % lanes
35 def LoadAndDuplicateOffsets(emitter, registers, lanes, offsets):
36 if lanes == 1 or lanes == 2 or lanes == 3:
38 for unused_i in range(0, lanes):
46 raise ConfigurationError('Unsupported number of lanes: %d' % lanes)
51 """Prepare lanes fo
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H A Dmul_Nx8_Mx8_neon.py22 self.lanes = []
25 self.lanes.append(lane)
28 for i in range(0, len(self.lanes)):
29 registers.FreeRegister(self.lanes[i])
30 self.lanes[i] = None
34 lanes = MulLanes(address)
36 lanes.AddLane(registers.DoubleRegister())
37 return lanes
41 lanes = MulLanes(address)
42 lanes
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H A Dmul_1x8_Mx8_neon.py17 emitter.EmitComment('General 1xM lanes loop.')
197 def BuildName(result_type, lhs_add, rhs_add, lanes):
198 name = 'mul_1x8_%dx8_%s' % (lanes, result_type)
279 for lanes in range(1, 5):
280 GenerateMul1x8Mx8(emitter, result_type, lhs_add, rhs_add, lanes)
H A Dneon_emitter_64.py191 lanes = list(set([register.lane for register in registers]))
192 if len(lanes) > 1:
193 raise ArgumentError('Cannot mix lanes on a register list.')
196 if lanes[0] is None:
198 elif lanes[0] is -1:
205 return '{%s}[%d]' % (', '.join(map(str, typed_registers_nolane)), lanes[0])
/external/gemmlowp/meta/
H A Dtest_streams_correctness.cc105 template <int lanes, int leftover>
116 prepare_row_major_data(lanes, all_elements, stride, in);
117 Stream<std::uint8_t, lanes, 8, leftover, RowMajorWithSum>::Pack(in, params,
119 if (check(out, lanes, all_elements)) {
120 // std::cout << "Row: " << lanes << "x8x" << leftover << " : "
124 std::cout << "Row: " << lanes << "x8x" << leftover << " : "
131 for (int stride = lanes; stride < lanes + 4; ++stride) {
138 prepare_column_major_data(lanes, all_elements, stride, in);
139 Stream<std::uint8_t, lanes,
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H A Dbase.h97 static int Scratch(const StreamType& params, int lanes);
/external/trappy/tests/trappy/plotter/
H A DEventPlot.py78 :param num_lanes: Total number of expected lanes
90 :param lanes: The sorted order of lanes
91 :type lanes: list
122 lanes=None,
134 graph["lanes"] = self._get_lanes(lanes, lane_prefix, num_lanes, _data)
148 """Group data by lanes.
151 occuring simultaneously in different lanes.
185 """Populate the lanes fo
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/external/trappy/trappy/plotter/
H A DEventPlot.py78 :param num_lanes: Total number of expected lanes
90 :param lanes: The sorted order of lanes
91 :type lanes: list
122 lanes=None,
134 graph["lanes"] = self._get_lanes(lanes, lane_prefix, num_lanes, _data)
148 """Group data by lanes.
151 occuring simultaneously in different lanes.
185 """Populate the lanes fo
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/external/mesa3d/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_lowering_gm107.cpp120 // mov coordinates from lane l to all lanes
126 add->lanes = 1; /* abused for .ndv */
129 // add dPdx from lane l to lanes dx
134 add->lanes = 1; /* abused for .ndv */
137 // add dPdy from lane l to lanes dy
142 add->lanes = 1; /* abused for .ndv */
172 mov->lanes = 1 << l;
211 insn->lanes = 0; /* abused for !.ndv */
H A Dnv50_ir.cpp579 lanes = 0xf;
763 i->lanes = lanes;
H A Dnv50_ir_emit_nv50.cpp633 code[1] = 0x00200000 | (i->lanes << 14);
650 code[1] = 0x00200000 | (i->lanes << 14);
791 code[1] |= (i->lanes << 14);
2025 emitQUADOP(insn, insn->lanes, insn->subOp);
2100 if (i->join || i->lanes != 0xf || i->exit)
H A Dnv50_ir_emit_gk110.cpp2237 code[0] = 0x00000002 | (i->lanes << 14);
2251 code[1] |= i->lanes << 10;
2561 emitQUADOP(insn, insn->subOp, insn->lanes);
H A Dnv50_ir.h874 unsigned lanes : 4;
H A Dnv50_ir_build_util.cpp268 quadop->lanes = l;
H A Dnv50_ir_emit_gm107.cpp722 emitField(0x27, 4, insn->lanes);
726 emitField(0x0c, 4, insn->lanes);
1594 emitField(0x26, 1, insn->lanes); /* abused for .ndv */
/external/trappy/tests/trappy/plotter/js/
H A DEventPlot.js90 itemRects, items, colourAxis, tip, lanes;
94 lanes = d.lanes;
106 mainHeight = 50 * lanes.length - margin.top - margin.bottom;
135 ext = d3.extent(lanes, function (d) {
174 .data(lanes)
192 .data(lanes)
241 lanes: lanes,
715 var miniHeight = ePlot.lanes
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/external/trappy/trappy/plotter/js/
H A DEventPlot.js90 itemRects, items, colourAxis, tip, lanes;
94 lanes = d.lanes;
106 mainHeight = 50 * lanes.length - margin.top - margin.bottom;
135 ext = d3.extent(lanes, function (d) {
174 .data(lanes)
192 .data(lanes)
241 lanes: lanes,
715 var miniHeight = ePlot.lanes
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/external/tensorflow/tensorflow/core/profiler/internal/
H A Dtfprof_timeline.cc349 for (int64 i = 0; i < p->lanes.size(); ++i) {
350 const auto& lane = p->lanes[i];
366 l = p->lanes.size();
369 p->lanes.push_back(nlane);
371 p->lanes[l][start_time] = end_time;
H A Dtfprof_timeline.h69 std::vector<std::map<int64, int64>> lanes; member in class:tensorflow::tfprof::Process
/external/tensorflow/tensorflow/python/client/
H A Dtimeline.py400 """Assigns non-overlapping lanes for the activities on each device."""
403 lanes = [0]
406 for (i, lts) in enumerate(lanes):
409 lanes[l] = ns.all_start_micros + ns.all_end_rel_micros
412 l = len(lanes)
413 lanes.append(ns.all_start_micros + ns.all_end_rel_micros)
/external/libhevc/common/arm/
H A Dihevc_intra_pred_luma_dc.s215 vdup.16 q12, d11[0] @3*dc + 2 (moved to all lanes)
456 vdup.16 q12, d11[0] @3*dc + 2 (moved to all lanes)
/external/vixl/src/aarch64/
H A Doperands-aarch64.h198 // described. They do not consider the number of lanes that make up a vector.
201 // Check the number of lanes, ie. the format of the vector, using methods such
310 VRegister(unsigned code, unsigned size, unsigned lanes = 1)
311 : CPURegister(code, size, kVRegister), lanes_(lanes) {
379 // For consistency, we assert the number of lanes of these scalar registers,
401 VIXL_DEPRECATED("GetLanes", int lanes() const) { return GetLanes(); }
H A Dlogic-aarch64.cc1384 int lanes = LaneCountFromFormat(vform); local
1388 for (int i = 0; i < lanes; i += 2) {
1397 VIXL_ASSERT(((i >> 1) + (j * lanes / 2)) < kMaxLanesPerVector);
1398 result[(i >> 1) + (j * lanes / 2)] = dst_val;
1564 int lanes = LaneCountFromFormat(vform); local
1577 VIXL_ASSERT(((i >> 1) + (j * lanes / 2)) < kMaxLanesPerVector);
1578 result[(i >> 1) + (j * lanes / 2)] = dst_val;
/external/v8/src/arm/
H A Dmacro-assembler-arm.cc1187 Register scratch, NeonSize size, uint32_t lanes) {
1190 DCHECK_IMPLIES(size == Neon32, lanes < 0xFFFFu);
1192 switch (lanes) {
1210 int lane_code = src.code() * 4 + (lanes & 0xF);
1220 case 0x2301: // Swap lanes 0, 1 and lanes 2, 3.
1232 int lane = (lanes >> (i * 4) & 0xF);

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