Searched refs:ld2 (Results 1 - 25 of 25) sorted by relevance

/external/libhevc/decoder/arm64/
H A Dihevcd_itrans_recon_dc_chroma.s117 ld2 {v2.8b, v3.8b},[x7],x2
118 ld2 {v4.8b, v5.8b},[x7],x2
119 ld2 {v6.8b, v7.8b},[x7],x2
120 ld2 {v8.8b, v9.8b},[x7],x2
122 ld2 {v10.8b, v11.8b},[x7],x2
123 ld2 {v12.8b, v13.8b},[x7],x2
124 ld2 {v14.8b, v15.8b},[x7],x2
125 ld2 {v16.8b, v17.8b},[x7]
184 ld2 {v2.8b, v3.8b},[x0],x2
185 ld2 {v
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H A Dihevcd_fmt_conv_420sp_to_420p.s173 ld2 {v0.8b, v1.8b},[x1],#16
189 ld2 {v0.8b, v1.8b}, [x1],#16
/external/libhevc/common/arm64/
H A Dihevc_intra_pred_chroma_mode2.s123 ld2 {v0.8b, v1.8b},[x0],x8
129 ld2 {v2.8b, v3.8b},[x10],x8
132 ld2 {v4.8b, v5.8b},[x0],x8
133 ld2 {v6.8b, v7.8b},[x10],x8
136 ld2 {v8.8b, v9.8b},[x0],x8
137 ld2 {v10.8b, v11.8b},[x10],x8
138 ld2 {v12.8b, v13.8b},[x0],x8
141 ld2 {v14.8b, v15.8b},[x10],x8
188 ld2 {v0.8b, v1.8b},[x0],x8
191 ld2 {v
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H A Dihevc_intra_pred_chroma_dc.s131 ld2 {v30.8b, v31.8b}, [x6], #16 //load from src[nt]
137 ld2 {v26.8b, v27.8b}, [x8],#16 //load from src[2nt+1]
159 ld2 {v30.8b, v31.8b}, [x6],#16 //load from src[nt]
163 ld2 {v26.8b, v27.8b}, [x8],#16 //load from src[2nt+1]
255 ld2 {v30.8b, v31.8b},[x6] //load from src[nt]
258 ld2 {v26.8b, v27.8b},[x8] //load from src[2nt+1]
H A Dihevc_intra_pred_chroma_ver.s117 ld2 {v20.8b, v21.8b}, [x6],#16 //16 loads (col 0:15)
121 ld2 {v22.8b, v23.8b}, [x6] //16 loads (col 16:31)
186 ld2 {v20.8b, v21.8b}, [x6],#16 //16 loads (col 0:15)
190 ld2 {v22.8b, v23.8b}, [x6] //16 loads (col 16:31)
/external/llvm/test/MC/AArch64/
H A Dneon-simd-ldst-multi-elem.s369 ld2 { v0.16b, v1.16b }, [x0]
370 ld2 { v15.8h, v16.8h }, [x15]
371 ld2 { v31.4s, v0.4s }, [sp]
372 ld2 { v0.2d, v1.2d }, [x0]
373 ld2 { v0.8b, v1.8b }, [x0]
374 ld2 { v15.4h, v16.4h }, [x15]
375 ld2 { v31.2s, v0.2s }, [sp]
376 // CHECK: ld2 { v0.16b, v1.16b }, [x0] // encoding: [0x00,0x80,0x40,0x4c]
377 // CHECK: ld2 { v15.8h, v16.8h }, [x15] // encoding: [0xef,0x85,0x40,0x4c]
378 // CHECK: ld2 { v3
[all...]
H A Dneon-simd-ldst-one-elem.s96 ld2 { v0.b, v1.b }[9], [x0]
97 ld2 { v15.h, v16.h }[7], [x15]
98 ld2 { v31.s, v0.s }[3], [sp]
99 ld2 { v0.d, v1.d }[1], [x0]
100 // CHECK: ld2 { v0.b, v1.b }[9], [x0] // encoding: [0x00,0x04,0x60,0x4d]
101 // CHECK: ld2 { v15.h, v16.h }[7], [x15] // encoding: [0xef,0x59,0x60,0x4d]
102 // CHECK: ld2 { v31.s, v0.s }[3], [sp] // encoding: [0xff,0x93,0x60,0x4d]
103 // CHECK: ld2 { v0.d, v1.d }[1], [x0] // encoding: [0x00,0x84,0x60,0x4d]
257 ld2 { v0.b, v1.b }[9], [x0], x3
258 ld2 { v1
[all...]
H A Dneon-simd-post-ldst-multi-elem.s124 ld2 { v0.16b, v1.16b }, [x0], x1
125 ld2 { v15.8h, v16.8h }, [x15], x2
126 ld2 { v31.4s, v0.4s }, [sp], #32
127 ld2 { v0.2d, v1.2d }, [x0], #32
128 ld2 { v0.8b, v1.8b }, [x0], x2
129 ld2 { v15.4h, v16.4h }, [x15], x3
130 ld2 { v31.2s, v0.2s }, [sp], #16
131 // CHECK: ld2 { v0.16b, v1.16b }, [x0], x1
133 // CHECK: ld2 { v15.8h, v16.8h }, [x15], x2
135 // CHECK: ld2 { v3
[all...]
H A Darm64-simd-ldst.s187 ld2.8b {v4, v5}, [x19]
188 ld2.16b {v4, v5}, [x19]
189 ld2.4h {v4, v5}, [x19]
190 ld2.8h {v4, v5}, [x19]
191 ld2.2s {v4, v5}, [x19]
192 ld2.4s {v4, v5}, [x19]
193 ld2.2d {v4, v5}, [x19]
205 ; CHECK: ld2.8b { v4, v5 }, [x19] ; encoding: [0x64,0x82,0x40,0x0c]
206 ; CHECK: ld2.16b { v4, v5 }, [x19] ; encoding: [0x64,0x82,0x40,0x4c]
207 ; CHECK: ld2
[all...]
H A Dneon-diagnostics.s3962 ld2 {v15.8h, v16.4h}, [x15]
3963 ld2 {v0.8b, v2.8b}, [x0]
3964 ld2 {v15.4h, v16.4h, v17.4h}, [x32]
3965 ld2 {v15.8h-v16.4h}, [x15]
3966 ld2 {v0.2d-v2.2d}, [x0]
3968 // CHECK-ERROR: ld2 {v15.8h, v16.4h}, [x15]
3971 // CHECK-ERROR: ld2 {v0.8b, v2.8b}, [x0]
3973 // CHECK-ERROR: ld2 {v15.4h, v16.4h, v17.4h}, [x32]
3976 // CHECK-ERROR: ld2 {v15.8h-v16.4h}, [x15]
3979 // CHECK-ERROR: ld2 {v
[all...]
/external/capstone/suite/MC/AArch64/
H A Dneon-simd-ldst-multi-elem.s.cs156 0x00,0x80,0x40,0x4c = ld2 {v0.16b, v1.16b}, [x0]
157 0xef,0x85,0x40,0x4c = ld2 {v15.8h, v16.8h}, [x15]
158 0xff,0x8b,0x40,0x4c = ld2 {v31.4s, v0.4s}, [sp]
159 0x00,0x8c,0x40,0x4c = ld2 {v0.2d, v1.2d}, [x0]
160 0x00,0x80,0x40,0x0c = ld2 {v0.8b, v1.8b}, [x0]
161 0xef,0x85,0x40,0x0c = ld2 {v15.4h, v16.4h}, [x15]
162 0xff,0x8b,0x40,0x0c = ld2 {v31.2s, v0.2s}, [sp]
163 0x00,0x80,0x40,0x4c = ld2 {v0.16b, v1.16b}, [x0]
164 0xef,0x85,0x40,0x4c = ld2 {v15.8h, v16.8h}, [x15]
165 0xff,0x8b,0x40,0x4c = ld2 {v3
[all...]
H A Dneon-simd-post-ldst-multi-elem.s.cs34 0x00,0x80,0xc1,0x4c = ld2 {v0.16b, v1.16b}, [x0], x1
35 0xef,0x85,0xc2,0x4c = ld2 {v15.8h, v16.8h}, [x15], x2
36 0xff,0x8b,0xdf,0x4c = ld2 {v31.4s, v0.4s}, [sp], #32
37 0x00,0x8c,0xdf,0x4c = ld2 {v0.2d, v1.2d}, [x0], #32
38 0x00,0x80,0xc2,0x0c = ld2 {v0.8b, v1.8b}, [x0], x2
39 0xef,0x85,0xc3,0x0c = ld2 {v15.4h, v16.4h}, [x15], x3
40 0xff,0x8b,0xdf,0x0c = ld2 {v31.2s, v0.2s}, [sp], #16
H A Dneon-simd-ldst-one-elem.s.cs38 0x00,0x04,0x60,0x4d = ld2 {v0.b, v1.b}[9], [x0]
39 0xef,0x59,0x60,0x4d = ld2 {v15.h, v16.h}[7], [x15]
40 0xff,0x93,0x60,0x4d = ld2 {v31.s, v0.s}[3], [sp]
41 0x00,0x84,0x60,0x4d = ld2 {v0.d, v1.d}[1], [x0]
102 0x00,0x04,0xe3,0x4d = ld2 {v0.b, v1.b}[9], [x0], x3
103 0xef,0x59,0xff,0x4d = ld2 {v15.h, v16.h}[7], [x15], #4
104 0xff,0x93,0xff,0x4d = ld2 {v31.s, v0.s}[3], [sp], #8
105 0x00,0x84,0xe0,0x4d = ld2 {v0.d, v1.d}[1], [x0], x0
/external/libavc/common/armv8/
H A Dih264_deblk_chroma_av8.s94 ld2 {v6.8b, v7.8b}, [x0], x1 //D6 = p1u , D7 = p1v
96 ld2 {v4.8b, v5.8b}, [x0], x1 //D4 = p0u , D5 = p0v
100 ld2 {v0.8b, v1.8b}, [x0], x1 //D0 = q0u , D1 = q0v
104 ld2 {v2.8b, v3.8b}, [x0] //D2 = q1u , D3 = q1v
344 ld2 {v6.8b, v7.8b}, [x0], x1 //Q3=p1
349 ld2 {v4.8b, v5.8b}, [x0], x1 //Q2=p0
354 ld2 {v0.8b, v1.8b}, [x0], x1 //Q0=q0
359 ld2 {v2.8b, v3.8b}, [x0] //Q1=q1
H A Dih264_ihadamard_scaling_av8.s220 ld2 {v0.4h, v1.4h}, [x0] //load 8 dc coeffs
H A Dih264_resi_trans_quant_av8.s622 ld2 {v0.4h-v1.4h}, [x0] //load src
/external/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc963 __ ld2(v21.V16B(), v22.V16B(), MemOperand(x0));
964 __ ld2(v21.V16B(), v22.V16B(), MemOperand(x1, x2, PostIndex));
965 __ ld2(v12.V16B(), v13.V16B(), MemOperand(x1, 32, PostIndex));
966 __ ld2(v14.V2D(), v15.V2D(), MemOperand(x0));
967 __ ld2(v0.V2D(), v1.V2D(), MemOperand(x1, x2, PostIndex));
968 __ ld2(v12.V2D(), v13.V2D(), MemOperand(x1, 32, PostIndex));
969 __ ld2(v27.V2S(), v28.V2S(), MemOperand(x0));
970 __ ld2(v2.V2S(), v3.V2S(), MemOperand(x1, x2, PostIndex));
971 __ ld2(v12.V2S(), v13.V2S(), MemOperand(x1, 16, PostIndex));
972 __ ld2(v
[all...]
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
H A Dnv50_ir_peephole.cpp3454 Instruction *ld2 = NULL; // can get at most 2 loads local
3522 ld2 = cloneShallow(func, ld1);
3523 updateLdStOffset(ld2, addr2, func);
3524 ld2->setType(typeOfSize(size2));
3526 ld2->setDef(d, (d < n2) ? def2[d] : NULL);
3528 ld1->bb->insertAfter(ld1, ld2);
/external/valgrind/none/tests/arm64/
H A Dmemory.stdout.exp9725 ld2 {v18.2d, v19.2d}, [x5] with x5 = middle_of_block+17, x6=7
9755 ld2 {v18.2d, v19.2d}, [x5], #32 with x5 = middle_of_block+9, x6=9
9785 ld2 {v18.2d, v19.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
9815 ld2 {v18.4s, v19.4s}, [x5] with x5 = middle_of_block+17, x6=7
9845 ld2 {v18.4s, v19.4s}, [x5], #32 with x5 = middle_of_block+9, x6=9
9875 ld2 {v18.4s, v19.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
9905 ld2 {v18.2s, v19.2s}, [x5] with x5 = middle_of_block+17, x6=7
9935 ld2 {v18.2s, v19.2s}, [x5], #16 with x5 = middle_of_block+9, x6=9
9965 ld2 {v18.2s, v19.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
9995 ld2 {v1
[all...]
/external/vixl/src/aarch64/
H A Dassembler-aarch64.h1926 void ld2(const VRegister& vt, const VRegister& vt2, const MemOperand& src);
1929 void ld2(const VRegister& vt,
H A Dmacro-assembler-aarch64.h2587 ld2(vt, vt2, src);
2595 ld2(vt, vt2, lane, src);
H A Dsimulator-aarch64.h1914 void ld2(VectorFormat vform,
1918 void ld2(VectorFormat vform,
H A Dsimulator-aarch64.cc3990 ld2(vf, ReadVRegister(reg[0]), ReadVRegister(reg[1]), addr[0]);
4242 ld2(vf, ReadVRegister(rt), ReadVRegister(rt2), lane, addr);
H A Dassembler-aarch64.cc1587 void Assembler::ld2(const VRegister& vt, function in class:vixl::aarch64::Assembler
1597 void Assembler::ld2(const VRegister& vt, function in class:vixl::aarch64::Assembler
H A Dlogic-aarch64.cc427 void Simulator::ld2(VectorFormat vform, function in class:vixl::aarch64::Simulator
444 void Simulator::ld2(VectorFormat vform, function in class:vixl::aarch64::Simulator

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