Searched refs:ld3 (Results 1 - 17 of 17) sorted by relevance

/external/llvm/test/MC/AArch64/
H A Dneon-simd-ldst-multi-elem.s402 ld3 { v0.16b, v1.16b, v2.16b }, [x0]
403 ld3 { v15.8h, v16.8h, v17.8h }, [x15]
404 ld3 { v31.4s, v0.4s, v1.4s }, [sp]
405 ld3 { v0.2d, v1.2d, v2.2d }, [x0]
406 ld3 { v0.8b, v1.8b, v2.8b }, [x0]
407 ld3 { v15.4h, v16.4h, v17.4h }, [x15]
408 ld3 { v31.2s, v0.2s, v1.2s }, [sp]
409 // CHECK: ld3 { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0x40,0x40,0x4c]
410 // CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15] // encoding: [0xef,0x45,0x40,0x4c]
411 // CHECK: ld3 { v3
[all...]
H A Dneon-simd-ldst-one-elem.s105 ld3 { v0.b, v1.b, v2.b }[9], [x0]
106 ld3 { v15.h, v16.h, v17.h }[7], [x15]
107 ld3 { v31.s, v0.s, v1.s }[3], [sp]
108 ld3 { v0.d, v1.d, v2.d }[1], [x0]
109 // CHECK: ld3 { v0.b, v1.b, v2.b }[9], [x0] // encoding: [0x00,0x24,0x40,0x4d]
110 // CHECK: ld3 { v15.h, v16.h, v17.h }[7], [x15] // encoding: [0xef,0x79,0x40,0x4d]
111 // CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp] // encoding: [0xff,0xb3,0x40,0x4d]
112 // CHECK: ld3 { v0.d, v1.d, v2.d }[1], [x0] // encoding: [0x00,0xa4,0x40,0x4d]
266 ld3 { v0.b, v1.b, v2.b }[9], [x0], #3
267 ld3 { v1
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H A Darm64-simd-ldst.s223 ld3.8b {v4, v5, v6}, [x19]
224 ld3.16b {v4, v5, v6}, [x19]
225 ld3.4h {v4, v5, v6}, [x19]
226 ld3.8h {v4, v5, v6}, [x19]
227 ld3.2s {v4, v5, v6}, [x19]
228 ld3.4s {v4, v5, v6}, [x19]
229 ld3.2d {v4, v5, v6}, [x19]
231 ld3.8b {v9, v10, v11}, [x9]
232 ld3.16b {v14, v15, v16}, [x19]
233 ld3
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H A Dneon-simd-post-ldst-multi-elem.s150 ld3 { v0.16b, v1.16b, v2.16b }, [x0], x1
151 ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2
152 ld3 { v31.4s, v0.4s, v1.4s }, [sp], #48
153 ld3 { v0.2d, v1.2d, v2.2d }, [x0], #48
154 ld3 { v0.8b, v1.8b, v2.8b }, [x0], x2
155 ld3 { v15.4h, v16.4h, v17.4h }, [x15], x3
156 ld3 { v31.2s, v0.2s, v1.2s }, [sp], #24
157 // CHECK: ld3 { v0.16b, v1.16b, v2.16b }, [x0], x1
159 // CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2
161 // CHECK: ld3 { v3
[all...]
H A Dneon-diagnostics.s3982 ld3 {v15.8h, v16.8h, v17.4h}, [x15]
3983 ld3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0]
3984 ld3 {v0.8b, v2.8b, v3.8b}, [x0]
3985 ld3 {v15.8h-v17.4h}, [x15]
3986 ld3 {v31.4s-v2.4s}, [sp]
3988 // CHECK-ERROR: ld3 {v15.8h, v16.8h, v17.4h}, [x15]
3991 // CHECK-ERROR: ld3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0]
3994 // CHECK-ERROR: ld3 {v0.8b, v2.8b, v3.8b}, [x0]
3997 // CHECK-ERROR: ld3 {v15.8h-v17.4h}, [x15]
4000 // CHECK-ERROR: ld3 {v3
[all...]
/external/capstone/suite/MC/AArch64/
H A Dneon-simd-ldst-multi-elem.s.cs170 0x00,0x40,0x40,0x4c = ld3 {v0.16b, v1.16b, v2.16b}, [x0]
171 0xef,0x45,0x40,0x4c = ld3 {v15.8h, v16.8h, v17.8h}, [x15]
172 0xff,0x4b,0x40,0x4c = ld3 {v31.4s, v0.4s, v1.4s}, [sp]
173 0x00,0x4c,0x40,0x4c = ld3 {v0.2d, v1.2d, v2.2d}, [x0]
174 0x00,0x40,0x40,0x0c = ld3 {v0.8b, v1.8b, v2.8b}, [x0]
175 0xef,0x45,0x40,0x0c = ld3 {v15.4h, v16.4h, v17.4h}, [x15]
176 0xff,0x4b,0x40,0x0c = ld3 {v31.2s, v0.2s, v1.2s}, [sp]
177 0x00,0x40,0x40,0x4c = ld3 {v0.16b, v1.16b, v2.16b}, [x0]
178 0xef,0x45,0x40,0x4c = ld3 {v15.8h, v16.8h, v17.8h}, [x15]
179 0xff,0x4b,0x40,0x4c = ld3 {v3
[all...]
H A Dneon-simd-post-ldst-multi-elem.s.cs41 0x00,0x40,0xc1,0x4c = ld3 {v0.16b, v1.16b, v2.16b}, [x0], x1
42 0xef,0x45,0xc2,0x4c = ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2
43 0xff,0x4b,0xdf,0x4c = ld3 {v31.4s, v0.4s, v1.4s}, [sp], #48
44 0x00,0x4c,0xdf,0x4c = ld3 {v0.2d, v1.2d, v2.2d}, [x0], #48
45 0x00,0x40,0xc2,0x0c = ld3 {v0.8b, v1.8b, v2.8b}, [x0], x2
46 0xef,0x45,0xc3,0x0c = ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3
47 0xff,0x4b,0xdf,0x0c = ld3 {v31.2s, v0.2s, v1.2s}, [sp], #24
H A Dneon-simd-ldst-one-elem.s.cs42 0x00,0x24,0x40,0x4d = ld3 {v0.b, v1.b, v2.b}[9], [x0]
43 0xef,0x79,0x40,0x4d = ld3 {v15.h, v16.h, v17.h}[7], [x15]
44 0xff,0xb3,0x40,0x4d = ld3 {v31.s, v0.s, v1.s}[3], [sp]
45 0x00,0xa4,0x40,0x4d = ld3 {v0.d, v1.d, v2.d}[1], [x0]
106 0x00,0x24,0xdf,0x4d = ld3 {v0.b, v1.b, v2.b}[9], [x0], #3
107 0xef,0x79,0xdf,0x4d = ld3 {v15.h, v16.h, v17.h}[7], [x15], #6
108 0xff,0xb3,0xc3,0x4d = ld3 {v31.s, v0.s, v1.s}[3], [sp], x3
109 0x00,0xa4,0xc6,0x4d = ld3 {v0.d, v1.d, v2.d}[1], [x0], x6
/external/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc1020 __ ld3(v20.V16B(), v21.V16B(), v22.V16B(), MemOperand(x0));
1021 __ ld3(v28.V16B(), v29.V16B(), v30.V16B(), MemOperand(x1, x2, PostIndex));
1022 __ ld3(v20.V16B(), v21.V16B(), v22.V16B(), MemOperand(x1, 48, PostIndex));
1023 __ ld3(v21.V2D(), v22.V2D(), v23.V2D(), MemOperand(x0));
1024 __ ld3(v18.V2D(), v19.V2D(), v20.V2D(), MemOperand(x1, x2, PostIndex));
1025 __ ld3(v27.V2D(), v28.V2D(), v29.V2D(), MemOperand(x1, 48, PostIndex));
1026 __ ld3(v7.V2S(), v8.V2S(), v9.V2S(), MemOperand(x0));
1027 __ ld3(v20.V2S(), v21.V2S(), v22.V2S(), MemOperand(x1, x2, PostIndex));
1028 __ ld3(v26.V2S(), v27.V2S(), v28.V2S(), MemOperand(x1, 24, PostIndex));
1029 __ ld3(v2
[all...]
/external/libjpeg-turbo/simd/
H A Djsimd_arm64_neon.S1873 ld3 {v10.8b, v11.8b, v12.8b}, [RGB], #24
1909 ld3 {v10.b, v11.b, v12.b}[0], [RGB], #3
1910 ld3 {v10.b, v11.b, v12.b}[1], [RGB], #3
1911 ld3 {v10.b, v11.b, v12.b}[2], [RGB], #3
1912 ld3 {v10.b, v11.b, v12.b}[3], [RGB], #3
1914 ld3 {v10.b, v11.b, v12.b}[4], [RGB], #3
1915 ld3 {v10.b, v11.b, v12.b}[5], [RGB], #3
1917 ld3 {v10.b, v11.b, v12.b}[6], [RGB], #3
/external/valgrind/none/tests/arm64/
H A Dmemory.stdout.exp10986 ld3 {v17.2d, v18.2d, v19.2d}, [x5] with x5 = middle_of_block+17, x6=7
11016 ld3 {v17.2d, v18.2d, v19.2d}, [x5], #48 with x5 = middle_of_block+9, x6=9
11046 ld3 {v17.2d, v18.2d, v19.2d}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
11076 ld3 {v17.4s, v18.4s, v19.4s}, [x5] with x5 = middle_of_block+17, x6=7
11106 ld3 {v17.4s, v18.4s, v19.4s}, [x5], #48 with x5 = middle_of_block+9, x6=9
11136 ld3 {v17.4s, v18.4s, v19.4s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
11166 ld3 {v17.2s, v18.2s, v19.2s}, [x5] with x5 = middle_of_block+17, x6=7
11196 ld3 {v17.2s, v18.2s, v19.2s}, [x5], #24 with x5 = middle_of_block+9, x6=9
11226 ld3 {v17.2s, v18.2s, v19.2s}, [x5], x6 with x5 = middle_of_block+-13, x6=-5
11256 ld3 {v1
[all...]
/external/vixl/src/aarch64/
H A Dassembler-aarch64.h1938 void ld3(const VRegister& vt,
1944 void ld3(const VRegister& vt,
H A Dmacro-assembler-aarch64.h2608 ld3(vt, vt2, vt3, src);
2617 ld3(vt, vt2, vt3, lane, src);
H A Dsimulator-aarch64.h1927 void ld3(VectorFormat vform,
1932 void ld3(VectorFormat vform,
H A Dsimulator-aarch64.cc4001 ld3(vf,
4254 ld3(vf,
H A Dassembler-aarch64.cc1618 void Assembler::ld3(const VRegister& vt, function in class:vixl::aarch64::Assembler
1629 void Assembler::ld3(const VRegister& vt, function in class:vixl::aarch64::Assembler
H A Dlogic-aarch64.cc471 void Simulator::ld3(VectorFormat vform, function in class:vixl::aarch64::Simulator
493 void Simulator::ld3(VectorFormat vform, function in class:vixl::aarch64::Simulator

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