| /external/llvm/test/MC/AArch64/ |
| H A D | neon-simd-ldst-one-elem.s | 46 ld3r { v0.16b, v1.16b, v2.16b }, [x0]
47 ld3r { v15.8h, v16.8h, v17.8h }, [x15]
48 ld3r { v31.4s, v0.4s, v1.4s }, [sp]
49 ld3r { v0.2d, v1.2d, v2.2d }, [x0]
50 ld3r { v0.8b, v1.8b, v2.8b }, [x0]
51 ld3r { v15.4h, v16.4h, v17.4h }, [x15]
52 ld3r { v31.2s, v0.2s, v1.2s }, [sp]
53 ld3r { v31.1d, v0.1d, v1.1d }, [sp]
54 // CHECK: ld3r { v0.16b, v1.16b, v2.16b }, [x0] // encoding: [0x00,0xe0,0x40,0x4d]
55 // CHECK: ld3r { v1
[all...] |
| H A D | arm64-simd-ldst.s | 958 ld3r: label
959 ld3r.8b {v4, v5, v6}, [x2]
960 ld3r.8b {v4, v5, v6}, [x2], x3
961 ld3r.16b {v4, v5, v6}, [x2]
962 ld3r.16b {v4, v5, v6}, [x2], x3
963 ld3r.4h {v4, v5, v6}, [x2]
964 ld3r.4h {v4, v5, v6}, [x2], x3
965 ld3r.8h {v4, v5, v6}, [x2]
966 ld3r.8h {v4, v5, v6}, [x2], x3
967 ld3r
[all...] |
| H A D | neon-diagnostics.s | 4195 ld3r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
4204 // CHECK-ERROR: ld3r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
4254 ld3r {v15.4h, v16.4h, v17.4h}, [x15], #1
4263 // CHECK-ERROR: ld3r {v15.4h, v16.4h, v17.4h}, [x15], #1
|
| /external/capstone/suite/MC/AArch64/ |
| H A D | neon-simd-ldst-one-elem.s.cs | 18 0x00,0xe0,0x40,0x4d = ld3r {v0.16b, v1.16b, v2.16b}, [x0]
19 0xef,0xe5,0x40,0x4d = ld3r {v15.8h, v16.8h, v17.8h}, [x15]
20 0xff,0xeb,0x40,0x4d = ld3r {v31.4s, v0.4s, v1.4s}, [sp]
21 0x00,0xec,0x40,0x4d = ld3r {v0.2d, v1.2d, v2.2d}, [x0]
22 0x00,0xe0,0x40,0x0d = ld3r {v0.8b, v1.8b, v2.8b}, [x0]
23 0xef,0xe5,0x40,0x0d = ld3r {v15.4h, v16.4h, v17.4h}, [x15]
24 0xff,0xeb,0x40,0x0d = ld3r {v31.2s, v0.2s, v1.2s}, [sp]
25 0xff,0xef,0x40,0x0d = ld3r {v31.1d, v0.1d, v1.1d}, [sp]
82 0x00,0xe0,0xc9,0x4d = ld3r {v0.16b, v1.16b, v2.16b}, [x0], x9
83 0xef,0xe5,0xc6,0x4d = ld3r {v1
[all...] |
| /external/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1053 __ ld3r(v24.V16B(), v25.V16B(), v26.V16B(), MemOperand(x0));
1054 __ ld3r(v24.V16B(), v25.V16B(), v26.V16B(), MemOperand(x1, x2, PostIndex));
1055 __ ld3r(v3.V16B(), v4.V16B(), v5.V16B(), MemOperand(x1, 3, PostIndex));
1056 __ ld3r(v4.V1D(), v5.V1D(), v6.V1D(), MemOperand(x0));
1057 __ ld3r(v7.V1D(), v8.V1D(), v9.V1D(), MemOperand(x1, x2, PostIndex));
1058 __ ld3r(v17.V1D(), v18.V1D(), v19.V1D(), MemOperand(x1, 24, PostIndex));
1059 __ ld3r(v16.V2D(), v17.V2D(), v18.V2D(), MemOperand(x0));
1060 __ ld3r(v20.V2D(), v21.V2D(), v22.V2D(), MemOperand(x1, x2, PostIndex));
1061 __ ld3r(v14.V2D(), v15.V2D(), v16.V2D(), MemOperand(x1, 24, PostIndex));
1062 __ ld3r(v1
[all...] |
| /external/valgrind/none/tests/arm64/ |
| H A D | memory.stdout.exp | 18641 ld3r {v17.2d , v18.2d , v19.2d }, [x5] with x5 = middle_of_block+3, x6=-5
18671 ld3r {v18.1d , v19.1d , v20.1d }, [x5] with x5 = middle_of_block+3, x6=-4
18701 ld3r {v17.4s , v18.4s , v19.4s }, [x5] with x5 = middle_of_block+3, x6=-3
18731 ld3r {v18.2s , v19.2s , v20.2s }, [x5] with x5 = middle_of_block+3, x6=-2
18761 ld3r {v17.8h , v18.8h , v19.8h }, [x5] with x5 = middle_of_block+3, x6=-5
18791 ld3r {v18.4h , v19.4h , v20.4h }, [x5] with x5 = middle_of_block+3, x6=-4
18821 ld3r {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+3, x6=-3
18851 ld3r {v18.8b , v19.8b , v20.8b }, [x5] with x5 = middle_of_block+3, x6=-2
18881 ld3r {v17.2d , v18.2d , v19.2d }, [x5], #24 with x5 = middle_of_block+3, x6=-5
18911 ld3r {v1
[all...] |
| /external/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 1951 void ld3r(const VRegister& vt,
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| H A D | macro-assembler-aarch64.h | 2625 ld3r(vt, vt2, vt3, src);
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| H A D | simulator-aarch64.h | 1938 void ld3r(VectorFormat vform,
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| H A D | simulator-aarch64.cc | 4191 ld3r(vf, ReadVRegister(rt), ReadVRegister(rt2), ReadVRegister(rt3), addr);
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| H A D | assembler-aarch64.cc | 1641 void Assembler::ld3r(const VRegister& vt, function in class:vixl::aarch64::Assembler
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| H A D | logic-aarch64.cc | 510 void Simulator::ld3r(VectorFormat vform, function in class:vixl::aarch64::Simulator
|