| /external/llvm/test/MC/AArch64/ |
| H A D | neon-simd-ldst-one-elem.s | 63 ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]
64 ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]
65 ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]
66 ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]
67 ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]
68 ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]
69 ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]
70 ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp]
71 // CHECK: ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0] // encoding: [0x00,0xe0,0x60,0x4d]
72 // CHECK: ld4r { v1
[all...] |
| H A D | arm64-simd-ldst.s | 1012 ld4r: label
1013 ld4r.8b {v4, v5, v6, v7}, [x2]
1014 ld4r.8b {v4, v5, v6, v7}, [x2], x3
1015 ld4r.16b {v4, v5, v6, v7}, [x2]
1016 ld4r.16b {v4, v5, v6, v7}, [x2], x3
1017 ld4r.4h {v4, v5, v6, v7}, [x2]
1018 ld4r.4h {v4, v5, v6, v7}, [x2], x3
1019 ld4r.8h {v4, v5, v6, v7}, [x2]
1020 ld4r.8h {v4, v5, v6, v7}, [x2], x3
1021 ld4r
[all...] |
| H A D | neon-diagnostics.s | 4196 ld4r {v31.2s, v0.2s, v1.2d, v2.2s}, [sp]
4207 // CHECK-ERROR: ld4r {v31.2s, v0.2s, v1.2d, v2.2s}, [sp]
4255 ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], sp
4266 // CHECK-ERROR: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], sp
|
| /external/capstone/suite/MC/AArch64/ |
| H A D | neon-simd-ldst-one-elem.s.cs | 26 0x00,0xe0,0x60,0x4d = ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0]
27 0xef,0xe5,0x60,0x4d = ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15]
28 0xff,0xeb,0x60,0x4d = ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp]
29 0x00,0xec,0x60,0x4d = ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
30 0x00,0xe0,0x60,0x0d = ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0]
31 0xef,0xe5,0x60,0x0d = ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15]
32 0xff,0xeb,0x60,0x0d = ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp]
33 0xff,0xef,0x60,0x0d = ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp]
90 0x00,0xe0,0xff,0x4d = ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], #4
91 0xef,0xe5,0xff,0x4d = ld4r {v1
[all...] |
| /external/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1146 __ ld4r(v14.V16B(), v15.V16B(), v16.V16B(), v17.V16B(), MemOperand(x0));
1147 __ ld4r(v13.V16B(),
1152 __ ld4r(v9.V16B(),
1157 __ ld4r(v8.V1D(), v9.V1D(), v10.V1D(), v11.V1D(), MemOperand(x0));
1158 __ ld4r(v4.V1D(),
1163 __ ld4r(v26.V1D(),
1168 __ ld4r(v19.V2D(), v20.V2D(), v21.V2D(), v22.V2D(), MemOperand(x0));
1169 __ ld4r(v28.V2D(),
1174 __ ld4r(v15.V2D(),
1179 __ ld4r(v3
[all...] |
| /external/valgrind/none/tests/arm64/ |
| H A D | memory.stdout.exp | 19362 ld4r {v17.2d , v18.2d , v19.2d , v20.2d }, [x5] with x5 = middle_of_block+3, x6=-5
19392 ld4r {v17.1d , v18.1d , v19.1d , v20.1d }, [x5] with x5 = middle_of_block+3, x6=-4
19422 ld4r {v17.4s , v18.4s , v19.4s , v20.4s }, [x5] with x5 = middle_of_block+3, x6=-3
19452 ld4r {v17.2s , v18.2s , v19.2s , v20.2s }, [x5] with x5 = middle_of_block+3, x6=-2
19482 ld4r {v17.8h , v18.8h , v19.8h , v20.8h }, [x5] with x5 = middle_of_block+3, x6=-5
19512 ld4r {v17.4h , v18.4h , v19.4h , v20.4h }, [x5] with x5 = middle_of_block+3, x6=-4
19542 ld4r {v17.16b, v18.16b, v19.16b, v20.16b}, [x5] with x5 = middle_of_block+3, x6=-3
19572 ld4r {v17.8b , v18.8b , v19.8b , v20.8b }, [x5] with x5 = middle_of_block+3, x6=-2
[all...] |
| /external/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 1972 void ld4r(const VRegister& vt,
|
| H A D | macro-assembler-aarch64.h | 2653 ld4r(vt, vt2, vt3, vt4, src);
|
| H A D | simulator-aarch64.h | 1956 void ld4r(VectorFormat vform,
|
| H A D | simulator-aarch64.cc | 4202 ld4r(vf,
|
| H A D | assembler-aarch64.cc | 1677 void Assembler::ld4r(const VRegister& vt, function in class:vixl::aarch64::Assembler
|
| H A D | logic-aarch64.cc | 576 void Simulator::ld4r(VectorFormat vform, function in class:vixl::aarch64::Simulator
|