/external/llvm/test/MC/ARM/ |
H A D | thumbv8m.s | 66 // CHECK: ldrexb r1, [r2] @ encoding: [0xd2,0xe8,0x4f,0x1f] 67 ldrexb r1, [r2] label
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H A D | basic-arm-instructions.s | 1193 ldrexb r3, [r4] 1198 @ CHECK: ldrexb r3, [r4] @ encoding: [0x9f,0x3f,0xd4,0xe1]
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H A D | basic-thumb2-instructions.s | 1056 ldrexb r5, [r7] 1063 @ CHECK: ldrexb r5, [r7] @ encoding: [0xd7,0xe8,0x4f,0x5f]
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/external/v8/src/arm/ |
H A D | assembler-arm.h | 1029 void ldrexb(Register dst, Register src, Condition cond = al);
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H A D | assembler-arm.cc | 2148 void Assembler::ldrexb(Register dst, Register src, Condition cond) { function in class:v8::internal::Assembler
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/external/vixl/src/aarch32/ |
H A D | assembler-aarch32.h | 2430 void ldrexb(Condition cond, Register rt, const MemOperand& operand); 2431 void ldrexb(Register rt, const MemOperand& operand) { function in class:vixl::aarch32::Assembler 2432 ldrexb(al, rt, operand);
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H A D | disasm-aarch32.h | 852 void ldrexb(Condition cond, Register rt, const MemOperand& operand);
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H A D | assembler-aarch32.cc | 5841 void Assembler::ldrexb(Condition cond, Register rt, const MemOperand& operand) { function in class:vixl::aarch32::Assembler 5864 Delegate(kLdrexb, &Assembler::ldrexb, cond, rt, operand);
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H A D | macro-assembler-aarch32.h | 2156 ldrexb(cond, rt, operand);
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H A D | disasm-aarch32.cc | 1756 void Disassembler::ldrexb(Condition cond, function in class:vixl::aarch32::Disassembler 10455 ldrexb(CurrentCond(), [all...] |
/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
H A D | basic-arm-instructions.s | 763 ldrexb r3, [r4] 768 @ CHECK: ldrexb r3, [r4] @ encoding: [0x9f,0x3f,0xd4,0xe1]
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H A D | basic-thumb2-instructions.s | 753 ldrexb r5, [r7] 760 @ CHECK: ldrexb r5, [r7] @ encoding: [0xd7,0xe8,0x4f,0x5f]
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/external/capstone/suite/MC/ARM/ |
H A D | basic-arm-instructions.s.cs | 328 0x9f,0x3f,0xd4,0xe1 = ldrexb r3, [r4]
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H A D | basic-thumb2-instructions.s.cs | 333 0xd7,0xe8,0x4f,0x5f = ldrexb r5, [r7]
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