| /external/capstone/arch/AArch64/ |
| H A D | AArch64Module.c | 14 MCRegisterInfo *mri; local
20 mri = cs_mem_malloc(sizeof(*mri));
22 AArch64_init(mri);
24 ud->printer_info = mri;
25 ud->getinsn_info = mri;
|
| /external/capstone/arch/Sparc/ |
| H A D | SparcModule.c | 14 MCRegisterInfo *mri; local
20 mri = cs_mem_malloc(sizeof(*mri));
22 Sparc_init(mri);
24 ud->printer_info = mri;
25 ud->getinsn_info = mri;
|
| /external/capstone/arch/SystemZ/ |
| H A D | SystemZModule.c | 14 MCRegisterInfo *mri; local
16 mri = cs_mem_malloc(sizeof(*mri));
18 SystemZ_init(mri);
20 ud->printer_info = mri;
21 ud->getinsn_info = mri;
|
| /external/capstone/arch/XCore/ |
| H A D | XCoreModule.c | 14 MCRegisterInfo *mri; local
16 mri = cs_mem_malloc(sizeof(*mri));
18 XCore_init(mri);
20 ud->printer_info = mri;
21 ud->getinsn_info = mri;
|
| /external/capstone/arch/Mips/ |
| H A D | MipsModule.c | 14 MCRegisterInfo *mri; local
22 mri = cs_mem_malloc(sizeof(*mri));
24 Mips_init(mri);
26 ud->printer_info = mri;
27 ud->getinsn_info = mri;
|
| /external/capstone/arch/PowerPC/ |
| H A D | PPCModule.c | 14 MCRegisterInfo *mri; local
21 mri = (MCRegisterInfo *) cs_mem_malloc(sizeof(*mri));
23 PPC_init(mri);
25 ud->printer_info = mri;
26 ud->getinsn_info = mri;
|
| /external/capstone/arch/ARM/ |
| H A D | ARMModule.c | 14 MCRegisterInfo *mri; local
21 mri = cs_mem_malloc(sizeof(*mri));
23 ARM_init(mri);
27 ud->printer_info = mri;
|
| /external/capstone/arch/X86/ |
| H A D | X86Module.c | 14 MCRegisterInfo *mri; local
20 mri = cs_mem_malloc(sizeof(*mri));
22 X86_init(mri);
27 ud->printer_info = mri;
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | RDFDeadCode.h | 36 DeadCodeElimination(DataFlowGraph &dfg, MachineRegisterInfo &mri) argument
37 : Trace(false), DFG(dfg), MRI(mri), LV(mri, dfg) {}
|
| H A D | RDFLiveness.h | 36 Liveness(MachineRegisterInfo &mri, const DataFlowGraph &g) argument
38 RAI(g.getRAI()), MRI(mri), Empty(), Trace(false) {}
|
| H A D | HexagonBitTracker.h | 26 HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri,
|
| H A D | HexagonBitSimplify.cpp | 1002 MachineRegisterInfo &mri)
1003 : Transformation(true), HII(hii), MRI(mri), BT(bt) {}
1317 MachineRegisterInfo &mri)
1318 : Transformation(true), HII(hii), MRI(mri), BT(bt) {}
1460 MachineRegisterInfo &mri)
1461 : Transformation(true), HII(hii), MRI(mri), BT(bt) {}
1474 CopyPropagation(const HexagonRegisterInfo &hri, MachineRegisterInfo &mri)
1475 : Transformation(false), MRI(mri) {}
1662 MachineRegisterInfo &mri)
1663 : Transformation(true), HII(hii), MRI(mri), B
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| H A D | CalcSpillWeights.cpp | 61 const MachineRegisterInfo &mri) {
79 const TargetRegisterClass *rc = mri.getRegClass(reg);
90 MachineRegisterInfo &mri = MF.getRegInfo(); local
104 bool noHint = mri.getRegAllocationHint(li.reg).first != 0;
109 for (MachineRegisterInfo::reg_iterator I = mri.reg_begin(li.reg);
141 unsigned hint = copyHint(mi, li.reg, tri, mri);
158 mri.setRegAllocationHint(li.reg, 0, hint);
59 copyHint(const MachineInstr *mi, unsigned reg, const TargetRegisterInfo &tri, const MachineRegisterInfo &mri) argument
|
| H A D | Spiller.cpp | 58 MachineRegisterInfo *mri; member in class:__anon22689::SpillerBase
68 mri = &mf.getRegInfo();
88 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
93 regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
103 } while (regItr != mri->reg_end() && (&*regItr == mi));
119 unsigned newVReg = mri->createVirtualRegister(trc);
|
| H A D | Splitter.h | 55 MachineRegisterInfo *mri; member in class:llvm::LoopSplitter
|
| H A D | RenderMachineFunction.h | 141 void setup(MachineFunction *mf, MachineRegisterInfo *mri,
169 MachineRegisterInfo *mri; member in class:llvm::TargetRegisterExtraInfo
246 MachineRegisterInfo *mri; member in class:llvm::RenderMachineFunction
|
| H A D | RegAllocPBQP.cpp | 132 MachineRegisterInfo *mri; member in class:__anon22653::RegAllocPBQP
146 void addStackInterval(const LiveInterval *spilled,MachineRegisterInfo* mri);
199 MachineRegisterInfo *mri = &mf->getRegInfo(); local
211 mri->setPhysRegUsed(itr->first);
221 const TargetRegisterClass *trc = mri->getRegClass(vreg);
492 MachineRegisterInfo* mri) {
499 const TargetRegisterClass *RC = mri->getRegClass(spilled->reg);
543 addStackInterval(spillInterval, mri);
586 const TargetRegisterClass *liRC = mri->getRegClass(li->reg);
645 mri
491 addStackInterval(const LiveInterval *spilled, MachineRegisterInfo* mri) argument
[all...] |
| H A D | RenderMachineFunction.cpp | 314 MachineRegisterInfo *mri,
318 this->mri = mri;
416 const TargetRegisterClass *regTRC = mri->getRegClass(reg);
920 mri = &mf->getRegInfo();
925 trei.setup(mf, mri, tri, lis);
950 for (MachineRegisterInfo::reg_iterator rItr = mri->reg_begin(li->reg),
951 rEnd = mri->reg_end();
313 setup(MachineFunction *mf, MachineRegisterInfo *mri, const TargetRegisterInfo *tri, LiveIntervals *lis) argument
|
| H A D | Splitter.cpp | 99 const TargetRegisterClass *trc = ls.mri->getRegClass(li.reg);
100 unsigned vreg = ls.mri->createVirtualRegister(trc);
278 mri = &mf->getRegInfo();
763 rItr = mri->reg_begin(split.getLI().reg),
764 rEnd = mri->reg_end();
|
| /external/llvm/lib/CodeGen/ |
| H A D | CalcSpillWeights.cpp | 48 const MachineRegisterInfo &mri) {
66 const TargetRegisterClass *rc = mri.getRegClass(reg);
132 MachineRegisterInfo &mri = MF.getRegInfo(); local
146 bool noHint = mri.getRegAllocationHint(li.reg).first != 0;
152 I = mri.reg_instr_begin(li.reg), E = mri.reg_instr_end();
185 unsigned hint = copyHint(mi, li.reg, tri, mri);
194 if (hweight > bestPhys && mri.isAllocatable(hint)) {
210 mri.setRegAllocationHint(li.reg, 0, hint);
46 copyHint(const MachineInstr *mi, unsigned reg, const TargetRegisterInfo &tri, const MachineRegisterInfo &mri) argument
|
| /external/llvm/include/llvm/MC/ |
| H A D | MCInstPrinter.h | 62 const MCRegisterInfo &mri)
63 : CommentStream(nullptr), MAI(mai), MII(mii), MRI(mri), UseMarkup(0),
61 MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii, const MCRegisterInfo &mri) argument
|
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | R600MCCodeEmitter.cpp | 41 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri) argument
42 : MCII(mcii), MRI(mri) { }
|
| H A D | SIMCCodeEmitter.cpp | 47 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri, argument
49 : MCII(mcii), MRI(mri) { }
|
| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| H A D | BPFMCCodeEmitter.cpp | 37 BPFMCCodeEmitter(const MCRegisterInfo &mri, bool IsLittleEndian) argument
38 : MRI(mri), IsLittleEndian(IsLittleEndian) {}
|
| /external/swiftshader/third_party/LLVM/lib/MC/ |
| H A D | MCContext.cpp | 30 MCContext::MCContext(const MCAsmInfo &mai, const MCRegisterInfo &mri, argument
32 MAI(mai), MRI(mri), MOFI(mofi),
|