Searched refs:reg3 (Results 1 - 25 of 46) sorted by relevance

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/external/libvpx/libvpx/vpx_ports/
H A Dasmdefs_mmi.h21 #define MMI_ADDU(reg1, reg2, reg3) \
22 "daddu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
30 #define MMI_SUBU(reg1, reg2, reg3) \
31 "dsubu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
50 #define MMI_ADDU(reg1, reg2, reg3) \
51 "addu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
59 #define MMI_SUBU(reg1, reg2, reg3) \
60 "subu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
/external/libvpx/libvpx/vpx_dsp/mips/
H A Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
51 DOTP_CONST_PAIR(reg5, reg3, cospi_12_64, cospi_20_64, reg5, reg3);
52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0);
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
67 DOTP_CONST_PAIR(reg4, reg3, cospi_14_64, cospi_18_64, reg4, reg3);
77 reg5 = reg7 + reg3;
78 reg7 = reg7 - reg3;
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
[all...]
H A Didct16x16_msa.c16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1,
24 reg2, reg3, reg4, reg5, reg6, reg7);
49 DOTP_CONST_PAIR(reg13, reg3, cospi_6_64, cospi_26_64, loc0, loc1);
50 BUTTERFLY_4(loc0, loc1, reg11, reg5, reg13, reg3, reg11, reg5);
52 loc1 = reg15 + reg3;
53 reg3 = reg15 - reg3;
85 DOTP_CONST_PAIR(reg3, reg1
110 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local
[all...]
/external/v8/src/interpreter/
H A Dbytecode-register.cc107 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, argument
112 if (reg3.is_valid() && reg2.index() + 1 != reg3.index()) {
115 if (reg4.is_valid() && reg3.index() + 1 != reg4.index()) {
H A Dbytecode-register.h66 Register reg3 = Register(),
/external/libyuv/files/source/
H A Drotate_msa.cc85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
99 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7);
121 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
147 res8 = (v16u8)__msa_ilvr_w((v4i32)reg7, (v4i32)reg3);
148 res9 = (v16u8)__msa_ilvl_w((v4i32)reg7, (v4i32)reg3);
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
180 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7);
202 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
[all...]
H A Drow_msa.cc481 v16u8 reg0, reg1, reg2, reg3; local
508 reg3 = (v16u8)__msa_pckev_b((v16i8)vec5, (v16i8)vec2);
510 dst0 = (v16u8)__msa_vshf_b(shuffler0, (v16i8)reg3, (v16i8)reg0);
511 dst1 = (v16u8)__msa_vshf_b(shuffler1, (v16i8)reg3, (v16i8)reg1);
512 dst2 = (v16u8)__msa_vshf_b(shuffler2, (v16i8)reg3, (v16i8)reg2);
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
793 reg3 = (v8u16)__msa_ilvev_b(zero, (v16i8)vec3);
799 reg3 *= const_0x81;
803 reg1 += reg3;
826 v8u16 reg0, reg1, reg2, reg3, reg local
1085 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; local
1159 v4u32 reg0, reg1, reg2, reg3; local
1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
1373 v4u32 reg0, reg1, reg2, reg3, rgba_scale; local
1506 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; local
1553 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1648 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1705 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1767 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local
1808 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local
1856 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local
1937 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local
2020 v8i16 reg0, reg1, reg2, reg3; local
2125 v8i16 reg0, reg1, reg2, reg3; local
2666 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local
2729 v4i32 reg0, reg1, reg2, reg3; local
[all...]
H A Dscale_msa.cc70 v8u16 reg0, reg1, reg2, reg3; local
85 reg3 = __msa_hadd_u_h(vec3, vec3);
87 reg1 += reg3;
133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
160 reg3 = __msa_hadd_u_h(vec3, vec3);
162 reg5 = (v8u16)__msa_pckev_d((v2i64)reg3, (v2i64)reg1);
164 reg7 = (v8u16)__msa_pckod_d((v2i64)reg3, (v2i64)reg1);
296 v4u32 reg0, reg1, reg2, reg3; local
334 reg3 = __msa_hadd_u_w(vec3, vec3);
338 reg3
[all...]
/external/elfutils/tests/
H A Drun-varlocs.sh68 [40051c,40052a) {reg3}
107 [400408,400421) {reg3}
H A Drun-addrcfi.sh36 integer reg3 (%ebx): same_value
83 integer reg3 (%ebx): same_value
135 integer reg3 (%rbx): undefined
201 integer reg3 (%rbx): undefined
305 integer reg3 (r3): undefined
1327 integer reg3 (r3): undefined
2355 integer reg3 (r3): undefined
3381 integer reg3 (%r3): undefined
3458 integer reg3 (%r3): undefined
3536 integer reg3 (r
[all...]
/external/valgrind/none/tests/s390x/
H A Dcksm.c27 register uint64_t reg3 asm("3") = len;
33 : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory");
36 len = reg3;
/external/vixl/src/aarch64/
H A Doperands-aarch64.h476 const CPURegister& reg3 = NoReg,
490 const CPURegister& reg3 = NoCPUReg,
503 const VRegister& reg3 = NoVReg,
513 const VRegister& reg3 = NoVReg,
522 CPURegister reg3 = NoCPUReg,
524 : list_(reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit()),
527 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
H A Dmacro-assembler-aarch64.cc2788 const Register& reg3,
2792 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit();
2802 const FPRegister& reg3,
2805 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit();
2822 const Register& reg3,
2825 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit();
2832 const FPRegister& reg3,
2835 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit();
2842 const CPURegister& reg3,
2847 const CPURegister regs[] = {reg1, reg2, reg3, reg
2786 Include(const Register& reg1, const Register& reg2, const Register& reg3, const Register& reg4) argument
2800 Include(const FPRegister& reg1, const FPRegister& reg2, const FPRegister& reg3, const FPRegister& reg4) argument
2820 Exclude(const Register& reg1, const Register& reg2, const Register& reg3, const Register& reg4) argument
2830 Exclude(const FPRegister& reg1, const FPRegister& reg2, const FPRegister& reg3, const FPRegister& reg4) argument
2840 Exclude(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4) argument
[all...]
H A Dassembler-aarch64.cc4750 const CPURegister& reg3,
4762 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
4789 const CPURegister& reg3,
4798 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
4810 const VRegister& reg3,
4815 match &= !reg3.IsValid() || reg3.IsSameFormat(reg1);
4823 const VRegister& reg3,
4833 if (!reg3
[all...]
H A Dmacro-assembler-aarch64.h3363 const Register& reg3 = NoReg,
3367 const VRegister& reg3 = NoVReg,
3377 const Register& reg3 = NoReg,
3381 const VRegister& reg3 = NoVReg,
3385 const CPURegister& reg3 = NoCPUReg,
/external/vixl/src/aarch32/
H A Dinstructions-aarch32.h465 RegisterList(Register reg1, Register reg2, Register reg3)
467 RegisterToList(reg3)) {}
468 RegisterList(Register reg1, Register reg2, Register reg3, Register reg4)
470 RegisterToList(reg3) | RegisterToList(reg4)) {}
554 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3)
556 RegisterToList(reg3)) {}
557 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3, VRegister reg4)
559 RegisterToList(reg3) | RegisterToList(reg4)) {}
H A Dmacro-assembler-aarch32.cc449 CPURegister reg3,
459 PushRegister(reg3);
466 uint32_t args = (reg4.GetType() << 12) | (reg3.GetType() << 8) |
471 int size = reg4.GetRegSizeInBytes() + reg3.GetRegSizeInBytes() +
492 if (reg3.GetType() == CPURegister::kRRegister) {
493 available_registers.Remove(Register(reg3.GetCode()));
507 PushRegister(reg3);
518 PreparePrintfArgument(reg3, &core_count, &vfp_count, &printf_type);
446 Printf(const char* format, CPURegister reg1, CPURegister reg2, CPURegister reg3, CPURegister reg4) argument
/external/v8/src/arm64/
H A Dassembler-arm64.h349 Register reg3 = NoReg,
357 const CPURegister& reg3 = NoReg,
370 const CPURegister& reg3 = NoCPUReg,
389 CPURegister reg3 = NoCPUReg,
391 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
393 DCHECK(AreSameSizeAndType(reg1, reg2, reg3, reg4));
H A Dassembler-arm64.cc213 Register reg3, Register reg4) {
214 CPURegList regs(reg1, reg2, reg3, reg4);
228 const CPURegister& reg3, const CPURegister& reg4,
237 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
265 const CPURegister& reg3, const CPURegister& reg4,
271 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
212 GetAllocatableRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4) argument
227 AreAliased(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument
264 AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument
/external/v8/src/full-codegen/
H A Dfull-codegen.h304 void PushOperands(Register reg1, Register reg2, Register reg3);
305 void PushOperands(Register reg1, Register reg2, Register reg3, Register reg4);
/external/v8/src/arm/
H A Dmacro-assembler-arm.cc3711 Register reg3,
3718 if (reg3.is_valid()) regs |= reg3.bit();
3737 Register reg3,
3744 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() +
3750 if (reg3.is_valid()) regs |= reg3.bit();
3709 GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6) argument
3735 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8) argument
H A Dmacro-assembler-arm.h66 Register reg3 = no_reg,
75 Register reg3 = no_reg,
/external/v8/src/ppc/
H A Dmacro-assembler-ppc.cc4237 Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, argument
4243 if (reg3.is_valid()) regs |= reg3.bit();
4260 bool AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, argument
4263 int n_of_valid_regs = reg1.is_valid() + reg2.is_valid() + reg3.is_valid() +
4271 if (reg3.is_valid()) regs |= reg3.bit();
H A Dmacro-assembler-ppc.h60 Register reg3 = no_reg,
67 bool AreAliased(Register reg1, Register reg2, Register reg3 = no_reg,
/external/elfutils/libdw/
H A Dknown-dwarf.h521 DWARF_ONE_KNOWN_DW_OP (reg3, DW_OP_reg3) \

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