| /external/llvm/test/MC/AArch64/ |
| H A D | neon-3vdiff.s | 401 rsubhn v0.8b, v1.8h, v2.8h
402 rsubhn v0.4h, v1.4s, v2.4s
403 rsubhn v0.2s, v1.2d, v2.2d
405 // CHECK: rsubhn v0.8b, v1.8h, v2.8h // encoding: [0x20,0x60,0x22,0x2e]
406 // CHECK: rsubhn v0.4h, v1.4s, v2.4s // encoding: [0x20,0x60,0x62,0x2e]
407 // CHECK: rsubhn v0.2s, v1.2d, v2.2d // encoding: [0x20,0x60,0xa2,0x2e]
|
| H A D | neon-diagnostics.s | 2819 rsubhn v0.8b, v1.8h, v2.8b
2820 rsubhn v0.4h, v1.4s, v2.4h
2821 rsubhn v0.2s, v1.2d, v2.2s
2824 // CHECK-ERROR: rsubhn v0.8b, v1.8h, v2.8b
2827 // CHECK-ERROR: rsubhn v0.4h, v1.4s, v2.4h
2830 // CHECK-ERROR: rsubhn v0.2s, v1.2d, v2.2s
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| /external/capstone/suite/MC/AArch64/ |
| H A D | neon-3vdiff.s.cs | 138 0x20,0x60,0x22,0x2e = rsubhn v0.8b, v1.8h, v2.8h
139 0x20,0x60,0x62,0x2e = rsubhn v0.4h, v1.4s, v2.4s
140 0x20,0x60,0xa2,0x2e = rsubhn v0.2s, v1.2d, v2.2d
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| /external/valgrind/none/tests/arm64/ |
| H A D | fp_and_simd.c | 2734 GEN_BINARY_TEST(rsubhn, 2s, 2d, 2d)
2736 GEN_BINARY_TEST(rsubhn, 4h, 4s, 4s)
2738 GEN_BINARY_TEST(rsubhn, 8b, 8h, 8h)
5367 // rsubhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
7796 rsubhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
8385 rsubhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
|
| H A D | fp_and_simd.stdout.exp | 26965 rsubhn v9.2s, v7.2d, v8.2d 05349f4ad2ee4133e08c964a68b6e61b d104a604b0404d63161107838b952a99 0000000000000000342ff946ca7b8ec7 fpsr=00000000
26967 rsubhn v9.4h, v7.4s, v8.4s 50ee42785838efb6f9983ba9b3a2dbfd 32e86dc600fde27927fcc446d6ce3061 00000000000000001e06573bd19bdcd5 fpsr=00000000
26969 rsubhn v9.8b, v7.8h, v8.8h 79526b3762c87e9a13f68777f17941ba b3cdbec4fee108e3cc21fd348f622409 0000000000000000c6ac6476488a621e fpsr=00000000
[all...] |
| /external/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1344 __ rsubhn(v15.V2S(), v25.V2D(), v4.V2D());
1345 __ rsubhn(v23.V4H(), v9.V4S(), v3.V4S());
1346 __ rsubhn(v6.V8B(), v30.V8H(), v24.V8H());
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| H A D | test-simulator-aarch64.cc | 4209 DEFINE_TEST_NEON_3DIFF_NARROW(rsubhn, Basic)
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| /external/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 2452 void rsubhn(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | macro-assembler-aarch64.h | 2201 V(rsubhn, Rsubhn) \
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| H A D | simulator-aarch64.h | 2734 V(rsubhn) \
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| H A D | simulator-aarch64.cc | 3670 rsubhn(vf, rd, rn, rm);
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| H A D | assembler-aarch64.cc | 1954 V(rsubhn, NEON_RSUBHN, vd.IsD()) \
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| H A D | logic-aarch64.cc | 3431 LogicVRegister Simulator::rsubhn(VectorFormat vform, function in class:vixl::aarch64::Simulator
|