| /external/libhevc/common/arm64/ |
| H A D | ihevc_inter_pred_luma_vert_w16inp_w16out.s | 211 shrn v19.4h, v19.4s, #6
230 shrn v20.4h, v20.4s, #6
257 shrn v21.4h, v21.4s, #6
275 shrn v31.4h, v31.4s, #6
302 shrn v19.4h, v19.4s, #6
323 shrn v20.4h, v20.4s, #6
345 shrn v21.4h, v21.4s, #6
360 shrn v31.4h, v31.4s, #6
374 shrn v19.4h, v19.4s, #6
387 shrn v2
[all...] |
| H A D | ihevc_intra_pred_chroma_mode_27_to_33.s | 143 shrn v5.8b, v2.8h,#5 //idx = pos >> 5
276 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
373 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
|
| H A D | ihevc_intra_pred_filters_chroma_mode_19_to_25.s | 256 shrn v5.8b, v2.8h,#5 //idx = pos >> 5
387 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
488 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
|
| H A D | ihevc_intra_pred_filters_luma_mode_19_to_25.s | 260 shrn v5.8b, v2.8h,#5 //idx = pos >> 5
387 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
487 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
|
| H A D | ihevc_intra_pred_luma_mode_27_to_33.s | 148 shrn v5.8b, v2.8h,#5 //idx = pos >> 5
281 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
379 shrn v3.8b, v2.8h,#5 //idx = pos >> 5
|
| /external/libavc/encoder/armv8/ |
| H A D | ih264e_half_pel_av8.s | 374 shrn v21.4h, v20.4s, #8 //// shift by 8 and later we will shift by 2 more with rounding (set2)
376 shrn v20.4h, v26.4s, #8 //// shift by 8 and later we will shift by 2 more with rounding (set1)
392 shrn v28.4h, v2.4s, #8 //// shift by 8 and later we will shift by 2 more with rounding (set3)
399 shrn v29.4h, v26.4s, #8 //// shift by 8 and later we will shift by 2 more with rounding (set4)
425 shrn v28.4h, v22.4s, #8 //// shift by 8 and later we will shift by 2 more with rounding (set5)
490 shrn v21.4h, v20.4s, #8 //// shift by 8 and later we will shift by 2 more with rounding (set2)
492 shrn v20.4h, v26.4s, #8 //// shift by 8 and later we will shift by 2 more with rounding (set1)
508 shrn v28.4h, v6.4s, #8 //// shift by 8 and later we will shift by 2 more with rounding (set3)
515 shrn v29.4h, v26.4s, #8 //// shift by 8 and later we will shift by 2 more with rounding (set4)
540 shrn v2
[all...] |
| /external/llvm/test/MC/AArch64/ |
| H A D | neon-simd-shift.s | 262 shrn v0.8b, v1.8h, #3
263 shrn v0.4h, v1.4s, #3
264 shrn v0.2s, v1.2d, #3
269 // CHECK: shrn v0.8b, v1.8h, #3 // encoding: [0x20,0x84,0x0d,0x0f]
270 // CHECK: shrn v0.4h, v1.4s, #3 // encoding: [0x20,0x84,0x1d,0x0f]
271 // CHECK: shrn v0.2s, v1.2d, #3 // encoding: [0x20,0x84,0x3d,0x0f]
|
| H A D | arm64-advsimd.s | 1473 shrn.8b v0, v0, #1
1475 shrn.4h v0, v0, #3
1477 shrn.2s v0, v0, #5
1645 ; CHECK: shrn.8b v0, v0, #1 ; encoding: [0x00,0x84,0x0f,0x0f]
1647 ; CHECK: shrn.4h v0, v0, #3 ; encoding: [0x00,0x84,0x1d,0x0f]
1649 ; CHECK: shrn.2s v0, v0, #5 ; encoding: [0x00,0x84,0x3b,0x0f]
1805 shrn v9.8b, v11.8h, #1
1807 shrn v7.4h, v8.4s, #3
1809 shrn v5.2s, v6.2d, #5
1875 ; CHECK: shrn
[all...] |
| H A D | neon-diagnostics.s | 1807 shrn v0.8b, v1.8b, #3
1808 shrn v0.4h, v1.4h, #3
1809 shrn v0.2s, v1.2s, #3
1815 // CHECK-ERROR: shrn v0.8b, v1.8b, #3
1818 // CHECK-ERROR: shrn v0.4h, v1.4h, #3
1821 // CHECK-ERROR: shrn v0.2s, v1.2s, #3
|
| /external/capstone/suite/MC/AArch64/ |
| H A D | neon-simd-shift.s.cs | 92 0x20,0x84,0x0d,0x0f = shrn v0.8b, v1.8h, #3
93 0x20,0x84,0x1d,0x0f = shrn v0.4h, v1.4s, #3
94 0x20,0x84,0x3d,0x0f = shrn v0.2s, v1.2d, #3
|
| /external/libjpeg-turbo/simd/ |
| H A D | jsimd_arm64_neon.S | 383 shrn v2.4h, v18.4s, #16 /* wsptr[DCTSIZE*0] = (int) DESCALE(tmp10 + tmp3, CONST_BITS+PASS1_BITS+3) */
384 shrn v9.4h, v20.4s, #16 /* wsptr[DCTSIZE*7] = (int) DESCALE(tmp10 - tmp3, CONST_BITS+PASS1_BITS+3) */
385 shrn v3.4h, v22.4s, #16 /* wsptr[DCTSIZE*1] = (int) DESCALE(tmp11 + tmp2, CONST_BITS+PASS1_BITS+3) */
386 shrn v8.4h, v24.4s, #16 /* wsptr[DCTSIZE*6] = (int) DESCALE(tmp11 - tmp2, CONST_BITS+PASS1_BITS+3) */
387 shrn v4.4h, v26.4s, #16 /* wsptr[DCTSIZE*2] = (int) DESCALE(tmp12 + tmp1, CONST_BITS+PASS1_BITS+3) */
388 shrn v7.4h, v28.4s, #16 /* wsptr[DCTSIZE*5] = (int) DESCALE(tmp12 - tmp1, CONST_BITS+PASS1_BITS+3) */
389 shrn v5.4h, v14.4s, #16 /* wsptr[DCTSIZE*3] = (int) DESCALE(tmp13 + tmp0, CONST_BITS+PASS1_BITS+3) */
390 shrn v6.4h, v16.4s, #16 /* wsptr[DCTSIZE*4] = (int) DESCALE(tmp13 - tmp0, CONST_BITS+PASS1_BITS+3) */
1980 shrn v22.4h, v18.4s, #16
1981 shrn v2
[all...] |
| /external/libavc/common/armv8/ |
| H A D | ih264_resi_trans_quant_av8.s | 524 shrn v0.4h, v22.4s, #1 //i4_value = (x0 + x1) >> 1;
526 shrn v1.4h, v24.4s, #1 //i4_value = (x0 - x1) >> 1;
|
| /external/vixl/src/aarch64/ |
| H A D | logic-aarch64.cc | 2564 LogicVRegister Simulator::shrn(VectorFormat vform, function in class:vixl::aarch64::Simulator
2719 return shrn(vform, dst, src, shift).UnsignedSaturate(vform);
3371 shrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
3415 shrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform));
|
| H A D | assembler-aarch64.h | 2272 void shrn(const VRegister& vd, const VRegister& vn, int shift);
|
| H A D | macro-assembler-aarch64.h | 2445 V(shrn, Shrn) \
|
| H A D | simulator-aarch64.h | 2654 LogicVRegister shrn(VectorFormat vform,
|
| H A D | simulator-aarch64.cc | 5040 shrn(vf, rd, rn, right_shift);
|
| H A D | assembler-aarch64.cc | 3755 void Assembler::shrn(const VRegister& vd, const VRegister& vn, int shift) {
|
| /external/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1423 __ shrn(v5.V2S(), v1.V2D(), 28);
1424 __ shrn(v29.V4H(), v18.V4S(), 7);
1425 __ shrn(v17.V8B(), v29.V8H(), 2);
|
| H A D | test-simulator-aarch64.cc | 4240 DEFINE_TEST_NEON_2OPIMM_NARROW(shrn, Basic, TypeWidth)
|
| /external/valgrind/none/tests/arm64/ |
| H A D | fp_and_simd.stdout.exp | 27477 shrn v4.2s, v29.2d, #1 a6cefa3960d0eb3c583bf063f17d3ac5 047df5176ac47402b403c88693212f5e 0000000000000000b5623a01499097af 047df5176ac47402b403c88693212f5e fpsr=00000000
27478 shrn v4.2s, v29.2d, #32 1850c415b5108a346d4910fe9c0f73dc 1cb60b0138474da0ed192ad765374833 00000000000000001cb60b01ed192ad7 1cb60b0138474da0ed192ad765374833 fpsr=00000000
27481 shrn v4.4h, v29.4s, #1 587f98cad298ff52421191af405932e3 695642a571fd70b12c4132841f2a16e6 00000000000000002152b85899420b73 695642a571fd70b12c4132841f2a16e6 fpsr=00000000
27482 shrn v4.4h, v29.4s, #16 fe0b20fc563632c0d88ab4d8979af518 3a76ac1293dc1412abdf6cd1012c2e68 00000000000000003a7693dcabdf012c 3a76ac1293dc1412abdf6cd1012c2e68 fpsr=00000000
27485 shrn v4.8b, v29.8h, #1 e3ce029b10daf0e146ad5f36033edbe7 33c644b4b911345f63416ded9fe6256d 0000000000000000e35a882fa0f6f3b6 33c644b4b911345f63416ded9fe6256d fpsr=00000000
27486 shrn v4.8b, v29.8h, #8 16aefb1449947d1e398a4437dfaa487b f21a8048f1ec91709f24c8f267f4472f 0000000000000000f280f1919fc86747 f21a8048f1ec91709f24c8f267f4472f fpsr=00000000
[all...] |