Searched refs:sqdmlsl2 (Results 1 - 14 of 14) sorted by relevance

/external/llvm/test/MC/AArch64/
H A Dneon-2velem.s158 sqdmlsl2 v0.4s, v1.8h, v1.h[2]
159 sqdmlsl2 v0.2d, v1.4s, v1.s[2]
160 sqdmlsl2 v0.2d, v1.4s, v22.s[2]
165 // CHECK: sqdmlsl2 v0.4s, v1.8h, v1.h[2] // encoding: [0x20,0x70,0x61,0x4f]
166 // CHECK: sqdmlsl2 v0.2d, v1.4s, v1.s[2] // encoding: [0x20,0x78,0x81,0x4f]
167 // CHECK: sqdmlsl2 v0.2d, v1.4s, v22.s[2] // encoding: [0x20,0x78,0x96,0x4f]
H A Dneon-3vdiff.s263 sqdmlsl2 v0.4s, v1.8h, v2.8h
264 sqdmlsl2 v0.2d, v1.4s, v2.4s
266 // CHECK: sqdmlsl2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0xb0,0x62,0x4e]
267 // CHECK: sqdmlsl2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0xb0,0xa2,0x4e]
H A Dneon-diagnostics.s2536 sqdmlsl2 v0.4s, v1.8s, v2.8h
2537 sqdmlsl2 v0.2d, v1.4d, v2.4s
2540 // CHECK-ERROR: sqdmlsl2 v0.4s, v1.8s, v2.8h
2543 // CHECK-ERROR: sqdmlsl2 v0.2d, v1.4d, v2.4s
2548 sqdmlsl2 v0.8h, v1.16b, v2.16b
2554 // CHECK-ERROR: sqdmlsl2 v0.8h, v1.16b, v2.16b
3341 sqdmlsl2 v0.4h, v1.8h, v1.h[2]
3342 sqdmlsl2 v0.4s, v1.8h, v1.h[8]
3343 sqdmlsl2 v0.4s, v1.8h, v16.h[2]
3344 sqdmlsl2 v
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H A Darm64-advsimd.s1246 sqdmlsl2.4s v0, v0, v0[1]
1248 sqdmlsl2.2d v0, v0, v0[3]
1315 ; CHECK: sqdmlsl2.4s v0, v0, v0[1] ; encoding: [0x00,0x70,0x50,0x4f]
1317 ; CHECK: sqdmlsl2.2d v0, v0, v0[3] ; encoding: [0x00,0x78,0xa0,0x4f]
/external/capstone/suite/MC/AArch64/
H A Dneon-2velem.s.cs63 0x20,0x70,0x61,0x4f = sqdmlsl2 v0.4s, v1.8h, v1.h[2]
64 0x20,0x78,0x81,0x4f = sqdmlsl2 v0.2d, v1.4s, v1.s[2]
65 0x20,0x78,0x96,0x4f = sqdmlsl2 v0.2d, v1.4s, v22.s[2]
H A Dneon-3vdiff.s.cs92 0x20,0xb0,0x62,0x4e = sqdmlsl2 v0.4s, v1.8h, v2.8h
93 0x20,0xb0,0xa2,0x4e = sqdmlsl2 v0.2d, v1.4s, v2.4s
/external/vixl/src/aarch64/
H A Dassembler-aarch64.h1700 void sqdmlsl2(const VRegister& vd,
2401 void sqdmlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
H A Dmacro-assembler-aarch64.h2229 V(sqdmlsl2, Sqdmlsl2) \
2413 V(sqdmlsl2, Sqdmlsl2) \
H A Dsimulator-aarch64.h2161 LogicVRegister sqdmlsl2(VectorFormat vform,
2761 V(sqdmlsl2) \
H A Dlogic-aarch64.cc1093 LogicVRegister Simulator::sqdmlsl2(VectorFormat vform, function in class:vixl::aarch64::Simulator
1101 return sqdmlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index));
3297 LogicVRegister Simulator::sqdmlsl2(VectorFormat vform, function in class:vixl::aarch64::Simulator
H A Dsimulator-aarch64.cc3619 sqdmlsl2(vf_l, rd, rn, rm);
3835 Op = &Simulator::sqdmlsl2;
H A Dassembler-aarch64.cc1930 V(sqdmlsl2, NEON_SQDMLSL2, vn.Is1H() || vn.Is1S() || vn.Is8H() || vn.Is4S()) \
3003 V(sqdmlsl2, NEON_SQDMLSL_byelement, vn.IsVector() && vn.IsQ()) \
/external/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc1554 __ sqdmlsl2(v12.V2D(), v7.V4S(), v22.V4S());
1555 __ sqdmlsl2(v20.V2D(), v25.V4S(), v8.S(), 0);
1556 __ sqdmlsl2(v25.V4S(), v26.V8H(), v18.V8H());
1557 __ sqdmlsl2(v25.V4S(), v19.V8H(), v5.H(), 0);
/external/valgrind/none/tests/arm64/
H A Dfp_and_simd.stdout.exp27994 sqdmlsl2 v29.2d, v20.4s, v3.s[1] 03f19a44ea019d8af8d2f00d3f7b429a 8fd52eb4cabe3a1b5aa1a19c1e8b9b28 c1783b8c4833302e08edd0664fcb7e67 0bc4ad4026f3e61afc89fee94b7b1516 8fd52eb4cabe3a1b5aa1a19c1e8b9b28 c1783b8c4833302e08edd0664fcb7e67 fpsr=00000000
27995 sqdmlsl2 v29.2d, v20.4s, v3.s[2] 1b609463a8a709981c0f2579bc5f388d e68e98b8b2f2ab63570295cba93eee5b 4fb9252ac361a716b70e746c301a0e9e 0f53f251f174b9f8f79193d5ac089989 e68e98b8b2f2ab63570295cba93eee5b 4fb9252ac361a716b70e746c301a0e9e fpsr=00000000
27998 sqdmlsl2 v29.4s, v20.8h, v3.h[1] afe3b06db513e73c6d50df51c27cc265 48d8d69a8b0aeeacb32640fbe71eadaa 1c11424efb5ee111e83961791bcc6d0f a012082dbe1165cc7fffffffc6401845 48d8d69a8b0aeeacb32640fbe71eadaa 1c11424efb5ee111e83961791bcc6d0f fpsr=08000000
27999 sqdmlsl2 v29.4s, v20.8h, v3.h[1] a431a60258024f7cdffb2e6be9685927 c445afc9cf651ed66457c7d7643fab28 5f3a8405529970f7bdc0617a4fcde10e c96eb9807ffffffffe48b0a9d62ee26b c445afc9cf651ed66457c7d7643fab28 5f3a8405529970f7bdc0617a4fcde10e fpsr=08000000
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