Searched refs:sqshlu (Results 1 - 16 of 16) sorted by relevance

/external/llvm/test/MC/AArch64/
H A Dneon-scalar-shift-imm.s97 sqshlu b15, b18, #6
98 sqshlu h19, h17, #6
99 sqshlu s16, s14, #25
100 sqshlu d11, d13, #32
102 // CHECK: sqshlu b15, b18, #6 // encoding: [0x4f,0x66,0x0e,0x7f]
103 // CHECK: sqshlu h19, h17, #6 // encoding: [0x33,0x66,0x16,0x7f]
104 // CHECK: sqshlu s16, s14, #25 // encoding: [0xd0,0x65,0x39,0x7f]
105 // CHECK: sqshlu d11, d13, #32 // encoding: [0xab,0x65,0x60,0x7f]
H A Dneon-simd-shift.s201 sqshlu v0.8b, v1.8b, #3
202 sqshlu v0.4h, v1.4h, #3
203 sqshlu v0.2s, v1.2s, #3
204 sqshlu v0.16b, v1.16b, #3
205 sqshlu v0.8h, v1.8h, #3
206 sqshlu v0.4s, v1.4s, #3
207 sqshlu v0.2d, v1.2d, #3
209 // CHECK: sqshlu v0.8b, v1.8b, #3 // encoding: [0x20,0x64,0x0b,0x2f]
210 // CHECK: sqshlu v0.4h, v1.4h, #3 // encoding: [0x20,0x64,0x13,0x2f]
211 // CHECK: sqshlu v
[all...]
H A Darm64-advsimd.s1360 sqshlu b0, b0, #1
1361 sqshlu h0, h0, #2
1362 sqshlu s0, s0, #3
1363 sqshlu d0, d0, #4
1409 ; CHECK: sqshlu b0, b0, #1 ; encoding: [0x00,0x64,0x09,0x7f]
1410 ; CHECK: sqshlu h0, h0, #2 ; encoding: [0x00,0x64,0x12,0x7f]
1411 ; CHECK: sqshlu s0, s0, #3 ; encoding: [0x00,0x64,0x23,0x7f]
1412 ; CHECK: sqshlu d0, d0, #4 ; encoding: [0x00,0x64,0x44,0x7f]
1498 sqshlu.8b v0, v0, #1
1499 sqshlu
[all...]
H A Dneon-diagnostics.s1708 sqshlu v0.8b, v1.8h, #3
1709 sqshlu v0.4h, v1.4s, #3
1710 sqshlu v0.2s, v1.2d, #3
1711 sqshlu v0.16b, v1.16b, #8
1712 sqshlu v0.8h, v1.8h, #16
1713 sqshlu v0.4s, v1.4s, #32
1714 sqshlu v0.2d, v1.2d, #64
1717 // CHECK-ERROR: sqshlu v0.8b, v1.8h, #3
1720 // CHECK-ERROR: sqshlu v0.4h, v1.4s, #3
1723 // CHECK-ERROR: sqshlu v
[all...]
/external/capstone/suite/MC/AArch64/
H A Dneon-scalar-shift-imm.s.cs19 0x4f,0x66,0x0e,0x7f = sqshlu b15, b18, #6
20 0x33,0x66,0x16,0x7f = sqshlu h19, h17, #6
21 0xd0,0x65,0x39,0x7f = sqshlu s16, s14, #25
22 0xab,0x65,0x60,0x7f = sqshlu d11, d13, #32
H A Dneon-simd-shift.s.cs71 0x20,0x64,0x0b,0x2f = sqshlu v0.8b, v1.8b, #3
72 0x20,0x64,0x13,0x2f = sqshlu v0.4h, v1.4h, #3
73 0x20,0x64,0x23,0x2f = sqshlu v0.2s, v1.2s, #3
74 0x20,0x64,0x0b,0x6f = sqshlu v0.16b, v1.16b, #3
75 0x20,0x64,0x13,0x6f = sqshlu v0.8h, v1.8h, #3
76 0x20,0x64,0x23,0x6f = sqshlu v0.4s, v1.4s, #3
77 0x20,0x64,0x43,0x6f = sqshlu v0.2d, v1.2d, #3
/external/valgrind/none/tests/arm64/
H A Dfp_and_simd.stdout.exp[all...]
/external/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc1656 __ sqshlu(b13, b14, 6);
1657 __ sqshlu(d0, d16, 44);
1658 __ sqshlu(h5, h29, 15);
1659 __ sqshlu(s29, s8, 13);
1660 __ sqshlu(v27.V16B(), v20.V16B(), 2);
1661 __ sqshlu(v24.V2D(), v12.V2D(), 11);
1662 __ sqshlu(v12.V2S(), v19.V2S(), 22);
1663 __ sqshlu(v8.V4H(), v12.V4H(), 11);
1664 __ sqshlu(v18.V4S(), v3.V4S(), 8);
1665 __ sqshlu(v
[all...]
H A Dtest-simulator-aarch64.cc4255 DEFINE_TEST_NEON_2OPIMM(sqshlu, Basic, TypeWidthFromZero)
4287 DEFINE_TEST_NEON_2OPIMM_SCALAR(sqshlu, Basic, TypeWidthFromZero)
/external/libjpeg-turbo/simd/
H A Djsimd_arm64_neon.S1600 sqshlu v21.8h, v20.8h, #8
1601 sqshlu v25.8h, v24.8h, #8
1602 sqshlu v29.8h, v28.8h, #8
1637 sqshlu v21.8h, v20.8h, #8
1638 sqshlu v25.8h, v24.8h, #8
1639 sqshlu v29.8h, v28.8h, #8
/external/vixl/src/aarch64/
H A Dsimulator-aarch64.cc4870 sqshlu(vf, rd, rn, left_shift);
4973 sqshlu(vf, rd, rn, left_shift);
H A Dassembler-aarch64.h2024 void sqshlu(const VRegister& vd, const VRegister& vn, int shift);
H A Dmacro-assembler-aarch64.h2453 V(sqshlu, Sqshlu) \
H A Dsimulator-aarch64.h2614 LogicVRegister sqshlu(VectorFormat vform,
H A Dassembler-aarch64.cc3647 void Assembler::sqshlu(const VRegister& vd, const VRegister& vn, int shift) {
H A Dlogic-aarch64.cc1752 LogicVRegister Simulator::sqshlu(VectorFormat vform, function in class:vixl::aarch64::Simulator

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