/external/llvm/test/MC/AArch64/ |
H A D | neon-scalar-shift-imm.s | 124 sqshrn b10, h15, #5 125 sqshrn h17, s10, #4 126 sqshrn s18, d10, #31 128 // CHECK: sqshrn b10, h15, #5 // encoding: [0xea,0x95,0x0b,0x5f] 129 // CHECK: sqshrn h17, s10, #4 // encoding: [0x51,0x95,0x1c,0x5f] 130 // CHECK: sqshrn s18, d10, #31 // encoding: [0x52,0x95,0x21,0x5f]
|
H A D | neon-simd-shift.s | 332 sqshrn v0.8b, v1.8h, #3 333 sqshrn v0.4h, v1.4s, #3 334 sqshrn v0.2s, v1.2d, #3 339 // CHECK: sqshrn v0.8b, v1.8h, #3 // encoding: [0x20,0x94,0x0d,0x0f] 340 // CHECK: sqshrn v0.4h, v1.4s, #3 // encoding: [0x20,0x94,0x1d,0x0f] 341 // CHECK: sqshrn v0.2s, v1.2d, #3 // encoding: [0x20,0x94,0x3d,0x0f]
|
H A D | arm64-advsimd.s | 1368 sqshrn b0, h0, #1 1369 sqshrn h0, s0, #2 1370 sqshrn s0, d0, #3 1417 ; CHECK: sqshrn b0, h0, #1 ; encoding: [0x00,0x94,0x0f,0x5f] 1418 ; CHECK: sqshrn h0, s0, #2 ; encoding: [0x00,0x94,0x1e,0x5f] 1419 ; CHECK: sqshrn s0, d0, #3 ; encoding: [0x00,0x94,0x3d,0x5f] 1512 sqshrn.8b v0, v0, #1 1514 sqshrn.4h v0, v0, #3 1516 sqshrn.2s v0, v0, #5 1684 ; CHECK: sqshrn [all...] |
H A D | neon-diagnostics.s | 1923 sqshrn v0.8b, v1.8b, #3 1924 sqshrn v0.4h, v1.4h, #3 1925 sqshrn v0.2s, v1.2s, #3 1931 // CHECK-ERROR: sqshrn v0.8b, v1.8b, #3 1934 // CHECK-ERROR: sqshrn v0.4h, v1.4h, #3 1937 // CHECK-ERROR: sqshrn v0.2s, v1.2s, #3 5095 sqshrn b10, h15, #99 5096 sqshrn h17, s10, #99 5097 sqshrn s18, d10, #99 5100 // CHECK-ERROR: sqshrn b1 [all...] |
/external/libhevc/common/arm64/ |
H A D | ihevc_inter_pred_chroma_vert_w16inp.s | 158 sqshrn v0.4h, v0.4s,#6 //right shift 159 sqshrn v30.4h, v7.4s,#6 //right shift 211 sqshrn v30.4h, v30.4s,#6 //right shift 221 sqshrn v28.4h, v28.4s,#6 //right shift 234 sqshrn v26.4h, v26.4s,#6 //right shift 248 sqshrn v24.4h, v24.4s,#6 //right shift 262 sqshrn v30.4h, v30.4s,#6 //right shift 275 sqshrn v28.4h, v28.4s,#6 //right shift 289 sqshrn v26.4h, v26.4s,#6 //right shift 305 sqshrn v2 [all...] |
H A D | ihevc_inter_pred_chroma_vert_w16inp_w16out.s | 158 sqshrn v0.4h, v0.4s,#6 //right shift 159 sqshrn v30.4h, v7.4s,#6 //right shift 209 sqshrn v30.4h, v30.4s,#6 //right shift 219 sqshrn v28.4h, v28.4s,#6 //right shift 232 sqshrn v26.4h, v26.4s,#6 //right shift 245 sqshrn v24.4h, v24.4s,#6 //right shift 258 sqshrn v30.4h, v30.4s,#6 //right shift 270 sqshrn v28.4h, v28.4s,#6 //right shift 283 sqshrn v26.4h, v26.4s,#6 //right shift 298 sqshrn v2 [all...] |
H A D | ihevc_inter_pred_filters_luma_vert_w16inp.s | 185 sqshrn v19.4h, v19.4s,#6 199 sqshrn v20.4h, v20.4s,#6 217 sqshrn v21.4h, v21.4s,#6 242 sqshrn v30.4h, v30.4s,#6 259 sqshrn v19.4h, v19.4s,#6 285 sqshrn v20.4h, v20.4s,#6 305 sqshrn v21.4h, v21.4s,#6 326 sqshrn v30.4h, v30.4s,#6 340 sqshrn v19.4h, v19.4s,#6 353 sqshrn v2 [all...] |
H A D | ihevc_deblk_luma_horz.s | 531 sqshrn v14.8b, v14.8h,#1 564 sqshrn v14.8b, v14.8h,#1
|
/external/capstone/suite/MC/AArch64/ |
H A D | neon-scalar-shift-imm.s.cs | 25 0xea,0x95,0x0b,0x5f = sqshrn b10, h15, #5 26 0x51,0x95,0x1c,0x5f = sqshrn h17, s10, #4 27 0x52,0x95,0x21,0x5f = sqshrn s18, d10, #31
|
H A D | neon-simd-shift.s.cs | 116 0x20,0x94,0x0d,0x0f = sqshrn v0.8b, v1.8h, #3 117 0x20,0x94,0x1d,0x0f = sqshrn v0.4h, v1.4s, #3 118 0x20,0x94,0x3d,0x0f = sqshrn v0.2s, v1.2d, #3
|
/external/libhevc/decoder/arm64/ |
H A D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 212 sqshrn v5.4h, v5.4s,#13 ////D8 = (U-128)*C4>>13 4 16-BIT VALUES 217 sqshrn v7.4h, v20.4s,#13 ////D10 = (V-128)*C1>>13 4 16-BIT VALUES 222 sqshrn v12.4h, v12.4s,#13 ////D12 = [(U-128)*C2 + (V-128)*C3]>>13 4 16-BIT VALUES 375 sqshrn v5.4h, v5.4s,#13 ////D8 = (U-128)*C4>>13 4 16-BIT VALUES 380 sqshrn v7.4h, v20.4s,#13 ////D10 = (V-128)*C1>>13 4 16-BIT VALUES 385 sqshrn v12.4h, v12.4s,#13 ////D12 = [(U-128)*C2 + (V-128)*C3]>>13 4 16-BIT VALUES
|
/external/libavc/common/armv8/ |
H A D | ih264_deblk_luma_av8.s | 168 sqshrn v29.8b, v28.8h, #1 // 169 sqshrn v28.8b, v10.8h, #1 //Q14 = i_macro_p1 176 sqshrn v31.8b, v30.8h, #1 // 177 sqshrn v30.8b, v4.8h, #1 //Q15 = i_macro_q1 571 sqshrn v24.8b, v24.8h, #1 //((p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1)) >> 1) L 572 sqshrn v25.8b, v26.8h, #1 //((p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1)) >> 1) H 592 sqshrn v18.8b, v18.8h, #1 //((q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1)) >> 1) L 594 sqshrn v19.8b, v20.8h, #1 //((q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1)) >> 1) H
|
/external/vixl/test/aarch64/ |
H A D | test-trace-aarch64.cc | 1667 __ sqshrn(b1, h28, 1); 1668 __ sqshrn(h31, s7, 10); 1669 __ sqshrn(s4, d10, 24); 1670 __ sqshrn(v10.V2S(), v1.V2D(), 29); 1671 __ sqshrn(v3.V4H(), v13.V4S(), 14); 1672 __ sqshrn(v27.V8B(), v6.V8H(), 7);
|
H A D | test-simulator-aarch64.cc | 4242 DEFINE_TEST_NEON_2OPIMM_NARROW(sqshrn, Basic, TypeWidth) 4275 DEFINE_TEST_NEON_2OPIMM_SCALAR_NARROW(sqshrn, Basic, TypeWidth)
|
/external/libjpeg-turbo/simd/ |
H A D | jsimd_arm64_neon.S | 940 sqshrn v28.8b, v16.8h, #5 942 sqshrn v29.8b, v17.8h, #5 944 sqshrn v30.8b, v18.8h, #5 946 sqshrn v31.8b, v19.8h, #5
|
/external/valgrind/none/tests/arm64/ |
H A D | fp_and_simd.stdout.exp | [all...] |
/external/vixl/src/aarch64/ |
H A D | simulator-aarch64.cc | 4906 sqshrn(vf, rd, rn, right_shift); 5068 sqshrn(vf, rd, rn, right_shift);
|
H A D | assembler-aarch64.h | 2296 void sqshrn(const VRegister& vd, const VRegister& vn, int shift);
|
H A D | macro-assembler-aarch64.h | 2454 V(sqshrn, Sqshrn) \
|
H A D | simulator-aarch64.h | 2686 LogicVRegister sqshrn(VectorFormat vform,
|
H A D | assembler-aarch64.cc | 3779 void Assembler::sqshrn(const VRegister& vd, const VRegister& vn, int shift) {
|
H A D | logic-aarch64.cc | 2747 LogicVRegister Simulator::sqshrn(VectorFormat vform, function in class:vixl::aarch64::Simulator
|