Searched refs:srsra (Results 1 - 16 of 16) sorted by relevance

/external/llvm/test/MC/AArch64/
H A Dneon-simd-shift.s123 srsra v0.8b, v1.8b, #3
124 srsra v0.4h, v1.4h, #3
125 srsra v0.2s, v1.2s, #3
126 srsra v0.16b, v1.16b, #3
127 srsra v0.8h, v1.8h, #3
128 srsra v0.4s, v1.4s, #3
129 srsra v0.2d, v1.2d, #3
131 // CHECK: srsra v0.8b, v1.8b, #3 // encoding: [0x20,0x34,0x0d,0x0f]
132 // CHECK: srsra v0.4h, v1.4h, #3 // encoding: [0x20,0x34,0x1d,0x0f]
133 // CHECK: srsra v
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H A Dneon-scalar-shift-imm.s50 srsra d15, d11, #19
52 // CHECK: srsra d15, d11, #19 // encoding: [0x6f,0x35,0x6d,0x5f]
H A Darm64-advsimd.s1376 srsra d0, d0, #1
1425 ; CHECK: srsra d0, d0, #1 ; encoding: [0x00,0x34,0x7f,0x5f]
1538 srsra.8b v0, v0, #1
1539 srsra.16b v0, v0, #2
1540 srsra.4h v0, v0, #3
1541 srsra.8h v0, v0, #4
1542 srsra.2s v0, v0, #5
1543 srsra.4s v0, v0, #6
1544 srsra.2d v0, v0, #7
1710 ; CHECK: srsra
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H A Dneon-diagnostics.s1576 srsra v0.8b, v1.8h, #3
1577 srsra v0.4h, v1.4s, #3
1578 srsra v0.2s, v1.2d, #3
1579 srsra v0.16b, v1.16b, #9
1580 srsra v0.8h, v1.8h, #17
1581 srsra v0.4s, v1.4s, #33
1582 srsra v0.2d, v1.2d, #65
1585 // CHECK-ERROR: srsra v0.8b, v1.8h, #3
1588 // CHECK-ERROR: srsra v0.4h, v1.4s, #3
1591 // CHECK-ERROR: srsra v
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/external/capstone/suite/MC/AArch64/
H A Dneon-simd-shift.s.cs44 0x20,0x34,0x0d,0x0f = srsra v0.8b, v1.8b, #3
45 0x20,0x34,0x1d,0x0f = srsra v0.4h, v1.4h, #3
46 0x20,0x34,0x3d,0x0f = srsra v0.2s, v1.2s, #3
47 0x20,0x34,0x0d,0x4f = srsra v0.16b, v1.16b, #3
48 0x20,0x34,0x1d,0x4f = srsra v0.8h, v1.8h, #3
49 0x20,0x34,0x3d,0x4f = srsra v0.4s, v1.4s, #3
50 0x20,0x34,0x7d,0x4f = srsra v0.2d, v1.2d, #3
H A Dneon-scalar-shift-imm.s.cs8 0x6f,0x35,0x6d,0x5f = srsra d15, d11, #19
/external/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc1744 __ srsra(d21, d30, 63);
1745 __ srsra(v27.V16B(), v30.V16B(), 6);
1746 __ srsra(v20.V2D(), v12.V2D(), 27);
1747 __ srsra(v0.V2S(), v17.V2S(), 5);
1748 __ srsra(v14.V4H(), v16.V4H(), 15);
1749 __ srsra(v18.V4S(), v3.V4S(), 20);
1750 __ srsra(v21.V8B(), v1.V8B(), 1);
1751 __ srsra(v31.V8H(), v25.V8H(), 2);
H A Dtest-simulator-aarch64.cc2280 // test for shift and accumulate instructions (srsra/ssra/usra/ursra).
4237 DEFINE_TEST_NEON_2OPIMM(srsra, Basic, TypeWidth)
4272 DEFINE_TEST_NEON_2OPIMM_SCALAR_D(srsra, Basic, TypeWidth)
/external/valgrind/none/tests/arm64/
H A Dfp_and_simd.stdout.exp[all...]
/external/vixl/src/aarch64/
H A Dsimulator-aarch64.cc4894 srsra(vf, rd, rn, right_shift);
4997 srsra(vf, rd, rn, right_shift);
H A Dassembler-aarch64.h2266 void srsra(const VRegister& vd, const VRegister& vn, int shift);
H A Dmacro-assembler-aarch64.h2460 V(srsra, Srsra) \
H A Dsimulator-aarch64.h2592 LogicVRegister srsra(VectorFormat vform,
H A Dassembler-aarch64.cc3743 void Assembler::srsra(const VRegister& vd, const VRegister& vn, int shift) {
H A Dlogic-aarch64.cc1831 LogicVRegister Simulator::srsra(VectorFormat vform, function in class:vixl::aarch64::Simulator
/external/swiftshader/third_party/LLVM/test/MC/ELF/
H A Dmany-section.s45402 .section srsra
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