Searched refs:sshll2 (Results 1 - 14 of 14) sorted by relevance

/external/llvm/test/MC/AArch64/
H A Dneon-shift-left-long.s11 sshll2 v0.8h, v1.16b, #3
12 sshll2 v0.4s, v1.8h, #3
13 sshll2 v0.2d, v1.4s, #3
18 // CHECK: sshll2 v0.8h, v1.16b, #3 // encoding: [0x20,0xa4,0x0b,0x4f]
19 // CHECK: sshll2 v0.4s, v1.8h, #3 // encoding: [0x20,0xa4,0x13,0x4f]
20 // CHECK: sshll2 v0.2d, v1.4s, #3 // encoding: [0x20,0xa4,0x23,0x4f]
H A Darm64-advsimd.s1546 sshll2.8h v0, v0, #2
1548 sshll2.4s v0, v0, #4
1550 sshll2.2d v0, v0, #6
1718 ; CHECK: sshll2.8h v0, v0, #2 ; encoding: [0x00,0xa4,0x0a,0x4f]
1720 ; CHECK: sshll2.4s v0, v0, #4 ; encoding: [0x00,0xa4,0x14,0x4f]
1722 ; CHECK: sshll2.2d v0, v0, #6 ; encoding: [0x00,0xa4,0x26,0x4f]
1854 sshll2 v10.8h, v3.16b, #6
1855 sshll2 v11.4s, v4.8h, #5
1856 sshll2 v12.2d, v5.4s, #4
1917 ; CHECK: sshll2
[all...]
H A Dneon-diagnostics.s1328 sshll2 v0.2d, v3.8s, #15
1336 sshll2 v0.8h, v1.16b, #9
1337 sshll2 v0.4s, v1.8h, #17
1347 // CHECK-ERROR: sshll2 v0.2d, v3.8s, #15
1365 // CHECK-ERROR: sshll2 v0.8h, v1.16b, #9
1368 // CHECK-ERROR: sshll2 v0.4s, v1.8h, #17
/external/capstone/suite/MC/AArch64/
H A Dneon-shift-left-long.s.cs5 0x20,0xa4,0x0b,0x4f = sshll2 v0.8h, v1.16b, #3
6 0x20,0xa4,0x13,0x4f = sshll2 v0.4s, v1.8h, #3
7 0x20,0xa4,0x23,0x4f = sshll2 v0.2d, v1.4s, #3
/external/valgrind/none/tests/arm64/
H A Dfp_and_simd.c4334 GEN_SHIFT_TEST(sshll2, 2d, 4s, 0)
4335 GEN_SHIFT_TEST(sshll2, 2d, 4s, 15)
4336 GEN_SHIFT_TEST(sshll2, 2d, 4s, 31)
4340 GEN_SHIFT_TEST(sshll2, 4s, 8h, 0)
4341 GEN_SHIFT_TEST(sshll2, 4s, 8h, 7)
4342 GEN_SHIFT_TEST(sshll2, 4s, 8h, 15)
4346 GEN_SHIFT_TEST(sshll2, 8h, 16b, 0)
4347 GEN_SHIFT_TEST(sshll2, 8h, 16b, 3)
4348 GEN_SHIFT_TEST(sshll2, 8h, 16b, 7)
H A Dfp_and_simd.stdout.exp[all...]
/external/libjpeg-turbo/simd/
H A Djsimd_arm64_neon.S292 sshll2 v23.4s, v22.8h, #(CONST_BITS) /* tmp0h tmp0 = LEFT_SHIFT(z2 + z3, CONST_BITS); */
297 sshll2 v27.4s, v26.8h, #(CONST_BITS) /* tmp1h tmp1 = LEFT_SHIFT(z2 - z3, CONST_BITS); */
552 sshll2 v23.4s, v22.8h, #(CONST_BITS) /* tmp0h tmp0 = LEFT_SHIFT(z2 + z3, CONST_BITS); */
555 sshll2 v27.4s, v26.8h, #(CONST_BITS) /* tmp1h tmp1 = LEFT_SHIFT(z2 - z3, CONST_BITS); */
631 sshll2 v23.4s, v22.8h, #(CONST_BITS) /* tmp0h tmp0 = LEFT_SHIFT(z2 + z3, CONST_BITS); */
636 sshll2 v27.4s, v26.8h, #(CONST_BITS) /* tmp1h tmp1 = LEFT_SHIFT(z2 - z3, CONST_BITS); */
/external/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc1763 __ sshll2(v10.V2D(), v4.V4S(), 14);
1764 __ sshll2(v26.V4S(), v31.V8H(), 6);
1765 __ sshll2(v3.V8H(), v26.V16B(), 4);
/external/vixl/src/aarch64/
H A Dassembler-aarch64.cc3663 void Assembler::sshll2(const VRegister& vd, const VRegister& vn, int shift) {
3675 sshll2(vd, vn, 0);
H A Dlogic-aarch64.cc1661 LogicVRegister Simulator::sshll2(VectorFormat vform, function in class:vixl::aarch64::Simulator
1685 return sshll2(vform, dst, src, shift);
H A Dassembler-aarch64.h2033 void sshll2(const VRegister& vd, const VRegister& vn, int shift);
H A Dmacro-assembler-aarch64.h2462 V(sshll2, Sshll2) \
H A Dsimulator-aarch64.h2550 LogicVRegister sshll2(VectorFormat vform,
H A Dsimulator-aarch64.cc5023 sshll2(vf, rd, rn, left_shift);

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