Searched refs:ssubl (Results 1 - 16 of 16) sorted by relevance

/external/libavc/common/armv8/
H A Dih264_ihadamard_scaling_av8.s111 ssubl v6.4s, v1.4h, v2.4h //x2 = x5 - x6
112 ssubl v7.4s, v0.4h, v3.4h //x3 = x4 - x7
225 ssubl v4.4s, v0.4h, v1.4h //i4_x1 = i4_x4 - i4_x5;...x3
H A Dih264_resi_trans_quant_av8.s487 ssubl v6.4s, v1.4h, v2.4h //x2 = x5 - x6;
488 ssubl v7.4s, v0.4h, v3.4h //x3 = x4 - x7;
635 ssubl v3.4s, v0.4h, v1.4h //x1 = x4 - x5; x3 = x6 - x7;
H A Dih264_iquant_itrans_recon_av8.s661 ssubl v22.4s, v13.4h, v11.4h
667 ssubl v26.4s, v15.4h, v9.4h
/external/libhevc/common/arm64/
H A Dihevc_itrans_recon_4x4.s150 ssubl v17.4s, v0.4h, v2.4h //pi2_src[0] - pi2_src[2]
184 ssubl v17.4s, v0.4h, v2.4h //pi2_src[0] - pi2_src[2]
/external/llvm/test/MC/AArch64/
H A Dneon-3vdiff.s49 ssubl v0.8h, v1.8b, v2.8b
50 ssubl v0.4s, v1.4h, v2.4h
51 ssubl v0.2d, v1.2s, v2.2s
53 // CHECK: ssubl v0.8h, v1.8b, v2.8b // encoding: [0x20,0x20,0x22,0x0e]
54 // CHECK: ssubl v0.4s, v1.4h, v2.4h // encoding: [0x20,0x20,0x62,0x0e]
55 // CHECK: ssubl v0.2d, v1.2s, v2.2s // encoding: [0x20,0x20,0xa2,0x0e]
H A Dneon-diagnostics.s2155 ssubl v0.8h, v1.8h, v2.8b
2156 ssubl v0.4s, v1.4s, v2.4h
2157 ssubl v0.2d, v1.2d, v2.2s
2160 // CHECK-ERROR: ssubl v0.8h, v1.8h, v2.8b
2163 // CHECK-ERROR: ssubl v0.4s, v1.4s, v2.4h
2166 // CHECK-ERROR: ssubl v0.2d, v1.2d, v2.2s
/external/capstone/suite/MC/AArch64/
H A Dneon-3vdiff.s.cs14 0x20,0x20,0x22,0x0e = ssubl v0.8h, v1.8b, v2.8b
15 0x20,0x20,0x62,0x0e = ssubl v0.4s, v1.4h, v2.4h
16 0x20,0x20,0xa2,0x0e = ssubl v0.2d, v1.2s, v2.2s
/external/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc1782 __ ssubl(v13.V2D(), v14.V2S(), v3.V2S());
1783 __ ssubl(v5.V4S(), v16.V4H(), v8.V4H());
1784 __ ssubl(v0.V8H(), v28.V8B(), v6.V8B());
H A Dtest-simulator-aarch64.cc4190 DEFINE_TEST_NEON_3DIFF_LONG(ssubl, Basic)
/external/vixl/src/aarch64/
H A Dassembler-aarch64.h2200 void ssubl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
H A Dmacro-assembler-aarch64.h2240 V(ssubl, Ssubl) \
H A Dsimulator-aarch64.h2456 LogicVRegister ssubl(VectorFormat vform,
H A Dsimulator-aarch64.cc3544 ssubl(vf_l, rd, rn, rm);
H A Dassembler-aarch64.cc1921 V(ssubl, NEON_SSUBL, vn.IsVector() && vn.IsD()) \
H A Dlogic-aarch64.cc2981 LogicVRegister Simulator::ssubl(VectorFormat vform, function in class:vixl::aarch64::Simulator
/external/valgrind/none/tests/arm64/
H A Dfp_and_simd.stdout.exp27387 ssubl v2.2d, v11.2s, v29.2s c0bf3e3313d664ac817f113b50530893 60921ac83a6c36e4107f13e2f25eff9a b0e19a224cb6cc3a76393fa0b0146c6e ffffffff9a45d44200000000424a932c 60921ac83a6c36e4107f13e2f25eff9a b0e19a224cb6cc3a76393fa0b0146c6e fpsr=00000000
27389 ssubl v2.4s, v11.4h, v29.4h f4a07ceaa4f2b31ac7cc39b68cac9064 34056b98e5c065346d522f714eb25698 99e1a2f4629b5cb61f4ab0eb3e7ed4a3 00004e0800007e8600001034000081f5 34056b98e5c065346d522f714eb25698 99e1a2f4629b5cb61f4ab0eb3e7ed4a3 fpsr=00000000
27391 ssubl v2.8h, v11.8b, v29.8b 1dd3711a86e3033416500deeec7fcde4 58840dd9b822ada82e148eb4a6b87abd 27a4912f78c71ece8204fce4a1d12077 00ac0010ff92ffd00005ffe7005aff46 58840dd9b822ada82e148eb4a6b87abd 27a4912f78c71ece8204fce4a1d12077 fpsr=00000000
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