| /external/llvm/test/MC/AArch64/ |
| H A D | neon-3vdiff.s | 333 ssubw v0.8h, v1.8h, v2.8b
334 ssubw v0.4s, v1.4s, v2.4h
335 ssubw v0.2d, v1.2d, v2.2s
337 // CHECK: ssubw v0.8h, v1.8h, v2.8b // encoding: [0x20,0x30,0x22,0x0e]
338 // CHECK: ssubw v0.4s, v1.4s, v2.4h // encoding: [0x20,0x30,0x62,0x0e]
339 // CHECK: ssubw v0.2d, v1.2d, v2.2s // encoding: [0x20,0x30,0xa2,0x0e]
|
| H A D | neon-diagnostics.s | 2703 ssubw v0.8h, v1.8h, v2.8h
2704 ssubw v0.4s, v1.4s, v2.4s
2705 ssubw v0.2d, v1.2d, v2.2d
2708 // CHECK-ERROR: ssubw v0.8h, v1.8h, v2.8h
2711 // CHECK-ERROR: ssubw v0.4s, v1.4s, v2.4s
2714 // CHECK-ERROR: ssubw v0.2d, v1.2d, v2.2d
|
| /external/libavc/common/armv8/ |
| H A D | ih264_iquant_itrans_recon_av8.s | 674 ssubw v22.4s, v22.4s, v15.4h
683 ssubw v28.4s, v28.4s, v11.4h
687 ssubw v22.4s, v22.4s, v21.4h
696 ssubw v28.4s, v28.4s, v18.4h
|
| /external/capstone/suite/MC/AArch64/ |
| H A D | neon-3vdiff.s.cs | 114 0x20,0x30,0x22,0x0e = ssubw v0.8h, v1.8h, v2.8b
115 0x20,0x30,0x62,0x0e = ssubw v0.4s, v1.4s, v2.4h
116 0x20,0x30,0xa2,0x0e = ssubw v0.2d, v1.2d, v2.2s
|
| /external/libhevc/common/arm64/ |
| H A D | ihevc_deblk_luma_horz.s | 509 ssubw v4.8h, v6.8h , v7.8b
563 ssubw v14.8h, v14.8h , v7.8b
|
| H A D | ihevc_deblk_luma_vert.s | 588 ssubw v2.8h, v2.8h , v20.8b
|
| /external/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1788 __ ssubw(v25.V2D(), v23.V2D(), v26.V2S());
1789 __ ssubw(v21.V4S(), v18.V4S(), v24.V4H());
1790 __ ssubw(v30.V8H(), v22.V8H(), v3.V8B());
|
| H A D | test-simulator-aarch64.cc | 4191 DEFINE_TEST_NEON_3DIFF_WIDE(ssubw, Basic)
|
| /external/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 2206 void ssubw(const VRegister& vd, const VRegister& vn, const VRegister& vm);
|
| H A D | macro-assembler-aarch64.h | 2242 V(ssubw, Ssubw) \
|
| H A D | simulator-aarch64.h | 2464 LogicVRegister ssubw(VectorFormat vform,
|
| H A D | simulator-aarch64.cc | 3646 ssubw(vf_l, rd, rn, rm);
|
| H A D | assembler-aarch64.cc | 2016 void Assembler::ssubw(const VRegister& vd,
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| H A D | logic-aarch64.cc | 3005 LogicVRegister Simulator::ssubw(VectorFormat vform, function in class:vixl::aarch64::Simulator
|
| /external/valgrind/none/tests/arm64/ |
| H A D | fp_and_simd.stdout.exp | 27435 ssubw v5.8h, v13.8h, v31.8b 61fa2da99ceb195cb6c3d92cc673cf9c 7cc351a5a62264bc6aa5b4e3cfd64d61 dcbaa15bf5a584d89a41d07661cedf5f 7d295164a65264466a44b515cff74d02 7cc351a5a62264bc6aa5b4e3cfd64d61 dcbaa15bf5a584d89a41d07661cedf5f fpsr=00000000
27437 ssubw v5.4s, v13.4s, v31.4h 4a1494510403422d9cbc639d09aec5de e72935cc478bbd1701ea2f6f17ee2276 d576418e24d15372fd2b0c7b11846ccd e72938a1478bb09c01ea1deb17edb5a9 e72935cc478bbd1701ea2f6f17ee2276 d576418e24d15372fd2b0c7b11846ccd fpsr=00000000
27439 ssubw v5.2d, v13.2d, v31.2s 5f495e87024af059299b8e24b791c21b 9235e7be120edf891a13a12e195003c4 86527e260eea6b74d457271b797f7136 9235e7be3db7b86e1a13a12d9fd0928e 9235e7be120edf891a13a12e195003c4 86527e260eea6b74d457271b797f7136 fpsr=00000000
[all...] |