| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| H A D | lp_bld_swizzle.h | 109 LLVMValueRef *swizzled);
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| H A D | lp_bld_swizzle.c | 318 * This fills a vector of dst_len length with the swizzled channels from src.
569 * @return the swizzled value.
599 * @param swizzled output swizzled values
605 LLVMValueRef *swizzled)
610 swizzled[chan] = lp_build_swizzle_soa_channel(bld, unswizzled,
602 lp_build_swizzle_soa(struct lp_build_context *bld, const LLVMValueRef *unswizzled, const unsigned char swizzles[4], LLVMValueRef *swizzled) argument
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| /external/mesa3d/src/gallium/drivers/nouveau/nv30/ |
| H A D | nv30_resource.h | 35 bool swizzled; member in struct:nv30_miptree
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| H A D | nv30_clear.c | 121 if (nv30_miptree(ps->texture)->swizzled) {
181 if (nv30_miptree(ps->texture)->swizzled) {
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| H A D | nv30_state.c | 373 /* Hardware can't handle different swizzled-ness or different blocksizes
381 if (color_mt->swizzled != zeta_mt->swizzled ||
382 (color_mt->swizzled &&
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| H A D | nv30_state_validate.c | 57 if (mt->swizzled)
70 if (nv30_miptree(fb->zsbuf->texture)->swizzled)
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| H A D | nv30_texture.c | 290 if (!mt->swizzled)
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| H A D | nv30_miptree.c | 102 if (mt->swizzled) {
422 mt->swizzled = true;
525 if (mt->swizzled)
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| /external/deqp/framework/common/ |
| H A D | tcuTexture.cpp | 1281 const Vec4 swizzled = swizzleRB(color, TextureFormat::RGB, m_format.order); local
1282 *((deUint16*)pixelPtr) = (deUint16)(PN(swizzled[0], 11, 5) | PN(swizzled[1], 5, 6) | PN(swizzled[2], 0, 5));
1288 const UVec4 swizzled = swizzleRB(color.cast<deUint32>(), TextureFormat::RGB, m_format.order); local
1289 *((deUint16*)pixelPtr) = (deUint16)(PU(swizzled[0], 11, 5) | PU(swizzled[1], 5, 6) | PU(swizzled[2], 0, 5));
1295 const Vec4 swizzled = swizzleRB(color, TextureFormat::RGB, m_format.order); local
1296 *((deUint16*)pixelPtr) = (deUint16)(PN(swizzled[
1302 const Vec4 swizzled = swizzleRB(color, TextureFormat::RGBA, m_format.order); local
1309 const UVec4 swizzled = swizzleRB(color.cast<deUint32>(), TextureFormat::RGBA, m_format.order); local
1316 const Vec4 swizzled = swizzleRB(color, TextureFormat::RGBA, m_format.order); local
1323 const Vec4 swizzled = color.swizzle(3,0,1,2); // RGBA -> ARGB local
1330 const UVec4 swizzled = swizzleRB(color.cast<deUint32>(), TextureFormat::RGBA, m_format.order); local
1430 const IVec4 swizzled = swizzleRB(color, TextureFormat::RGB, m_format.order); local
1437 const IVec4 swizzled = swizzleRB(color, TextureFormat::RGB, m_format.order); local
1445 const IVec4 swizzled = swizzleRB(color, TextureFormat::RGBA, m_format.order); local
1453 const IVec4 swizzled = swizzleRB(color, TextureFormat::RGBA, m_format.order); local
1460 const IVec4 swizzled = color.swizzle(3,0,1,2); // RGBA -> ARGB local
1468 const IVec4 swizzled = swizzleRB(color, TextureFormat::RGBA, m_format.order); local
1476 const IVec4 swizzled = swizzleRB(color, TextureFormat::RGBA, m_format.order); local
[all...] |
| /external/mesa3d/src/intel/vulkan/ |
| H A D | anv_gem.c | 228 bool swizzled = false; local
257 swizzled = get_tiling.swizzle_mode != I915_BIT_6_SWIZZLE_NONE;
265 return swizzled;
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| H A D | anv_device.c | 171 bool swizzled = anv_gem_get_bit6_swizzle(fd, I915_TILING_X); local
216 isl_device_init(&device->isl_dev, &device->info, swizzled);
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| /external/mesa3d/src/compiler/nir/ |
| H A D | nir_lower_tex.c | 633 nir_ssa_def *swizzled; local
640 swizzled = get_zero_or_one(b, tex->dest_type, swizzle[tex->component]);
648 swizzled = nir_swizzle(b, &tex->dest.ssa, swiz, 4, false);
658 swizzled = nir_vec(b, srcs, 4);
662 nir_ssa_def_rewrite_uses_after(&tex->dest.ssa, nir_src_for_ssa(swizzled),
663 swizzled->parent_instr);
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| /external/mesa3d/src/gallium/drivers/vc4/ |
| H A D | vc4_nir_lower_blend.c | 507 nir_ssa_def *swizzled[4]; local
509 swizzled[i] = vc4_nir_get_swizzled_channel(b, colors,
515 swizzled[0], swizzled[1],
516 swizzled[2], swizzled[3]));
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| /external/mesa3d/src/gallium/drivers/svga/ |
| H A D | svga_tgsi_vgpu10.c | 1489 * Create swizzled tgsi_full_src_register.
1496 struct tgsi_full_src_register swizzled = *reg; local
1498 swizzled.Register.SwizzleX = get_swizzle(reg, swizzleX);
1499 swizzled.Register.SwizzleY = get_swizzle(reg, swizzleY);
1500 swizzled.Register.SwizzleZ = get_swizzle(reg, swizzleZ);
1501 swizzled.Register.SwizzleW = get_swizzle(reg, swizzleW);
1502 return swizzled;
1507 * Create swizzled tgsi_full_src_register where all the swizzle
1513 struct tgsi_full_src_register swizzled = *reg; local
1515 swizzled
4896 boolean swizzled; member in struct:tex_swizzle_info
[all...] |
| /external/mesa3d/src/compiler/glsl/ |
| H A D | ir.cpp | 53 * \param from Component in the RHS that is to be swizzled
72 bool swizzled = false; local
103 swizzled = true;
106 if (swizzled) {
1380 * (i.e., float, int, unsigned, or bool) of the vector being swizzled,
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_alu.c | 166 struct rc_src_register swizzled = reg; local
167 swizzled.Swizzle = combine_swizzles4(reg.Swizzle, x, y, z, w);
168 return swizzled;
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| H A D | brw_vec4_visitor.cpp | 1111 src_reg swizzled(dest);
1112 swizzled.swizzle = BRW_SWIZZLE4(SWIZZLE_W, SWIZZLE_W,
1114 emit(MOV(dest, swizzled));
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| H A D | intel_mipmap_tree.c | 2369 intel_offset_S8(uint32_t stride, uint32_t x, uint32_t y, bool swizzled) argument
2394 if (swizzled) {
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