Searched refs:uaddl2 (Results 1 - 15 of 15) sorted by relevance

/external/libmpeg2/common/armv8/
H A Dicv_variance_av8.s93 uaddl2 v20.4s, v20.8h, v22.8h
94 uaddl2 v24.4s, v24.8h, v26.8h
/external/llvm/test/MC/AArch64/
H A Dneon-3vdiff.s41 uaddl2 v0.8h, v1.16b, v2.16b
42 uaddl2 v0.4s, v1.8h, v2.8h
43 uaddl2 v0.2d, v1.4s, v2.4s
45 // CHECK: uaddl2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0x00,0x22,0x6e]
46 // CHECK: uaddl2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0x00,0x62,0x6e]
47 // CHECK: uaddl2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0x00,0xa2,0x6e]
H A Darm64-advsimd.s2066 uaddl2 v9.8h, v13.16b, v14.16b
2068 uaddl2 v9.4s, v13.8h, v14.8h
2070 uaddl2 v9.2d, v13.4s, v14.4s
2072 ; CHECK: uaddl2.8h v9, v13, v14 ; encoding: [0xa9,0x01,0x2e,0x6e]
2074 ; CHECK: uaddl2.4s v9, v13, v14 ; encoding: [0xa9,0x01,0x6e,0x6e]
2076 ; CHECK: uaddl2.2d v9, v13, v14 ; encoding: [0xa9,0x01,0xae,0x6e]
H A Dneon-diagnostics.s2141 uaddl2 v0.8h, v1.16h, v2.16b
2142 uaddl2 v0.4s, v1.8s, v2.8h
2143 uaddl2 v0.2d, v1.4d, v2.4s
2146 // CHECK-ERROR: uaddl2 v0.8h, v1.16h, v2.16b
2149 // CHECK-ERROR: uaddl2 v0.4s, v1.8s, v2.8h
2152 // CHECK-ERROR: uaddl2 v0.2d, v1.4d, v2.4s
/external/capstone/suite/MC/AArch64/
H A Dneon-3vdiff.s.cs11 0x20,0x00,0x22,0x6e = uaddl2 v0.8h, v1.16b, v2.16b
12 0x20,0x00,0x62,0x6e = uaddl2 v0.4s, v1.8h, v2.8h
13 0x20,0x00,0xa2,0x6e = uaddl2 v0.2d, v1.4s, v2.4s
/external/libavc/common/armv8/
H A Dih264_intra_pred_luma_16x16_av8.s327 uaddl2 v3.8h, v0.16b, v1.16b
/external/libavc/encoder/armv8/
H A Dih264e_evaluate_intra16x16_modes_av8.s132 uaddl2 v3.8h, v0.16b, v1.16b
/external/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc2204 __ uaddl2(v5.V2D(), v23.V4S(), v6.V4S());
2205 __ uaddl2(v1.V4S(), v5.V8H(), v25.V8H());
2206 __ uaddl2(v22.V8H(), v30.V16B(), v28.V16B());
/external/vixl/src/aarch64/
H A Dassembler-aarch64.h2167 void uaddl2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
H A Dmacro-assembler-aarch64.h2256 V(uaddl2, Uaddl2) \
H A Dsimulator-aarch64.h2412 LogicVRegister uaddl2(VectorFormat vform,
H A Dsimulator-aarch64.cc3529 uaddl2(vf_l, rd, rn, rm);
H A Dassembler-aarch64.cc1924 V(uaddl2, NEON_UADDL2, vn.IsVector() && vn.IsQ()) \
H A Dlogic-aarch64.cc2855 LogicVRegister Simulator::uaddl2(VectorFormat vform, function in class:vixl::aarch64::Simulator
/external/valgrind/none/tests/arm64/
H A Dfp_and_simd.stdout.exp27382 uaddl2 v2.2d, v11.4s, v29.4s 52b73571557c52622fab85bf23c6ccce e484440f14df0338ef5a9979278f2c5a b08d0645aebeafc96111b32c8a5b085e 0000000195114a5400000000c39db301 e484440f14df0338ef5a9979278f2c5a b08d0645aebeafc96111b32c8a5b085e fpsr=00000000
27384 uaddl2 v2.4s, v11.8h, v29.8h d634de94bf2a68d55c2818405e15298f 3b4e64f4a9e03b9827d7407754b35a12 cd1ebe5740eb0ade55c852d23befc997 0001086c0001234b0000eacb00004676 3b4e64f4a9e03b9827d7407754b35a12 cd1ebe5740eb0ade55c852d23befc997 fpsr=00000000
27386 uaddl2 v2.8h, v11.16b, v29.16b 39dd6a423e27a49218fcc32356c26e69 e92bf4c9aa96ae065cde651d98a487e7 d03992df17cbfcb41e5dbf992fe5b5ec 01b90064018601a800c1016101aa00ba e92bf4c9aa96ae065cde651d98a487e7 d03992df17cbfcb41e5dbf992fe5b5ec fpsr=00000000
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