Searched refs:urecpe (Results 1 - 13 of 13) sorted by relevance

/external/llvm/test/MC/AArch64/
H A Dneon-simd-misc.s670 urecpe v6.4s, v8.4s
671 urecpe v4.2s, v0.2s
673 // CHECK: urecpe v6.4s, v8.4s // encoding: [0x06,0xc9,0xa1,0x4e]
674 // CHECK: urecpe v4.2s, v0.2s // encoding: [0x04,0xc8,0xa1,0x0e]
H A Dneon-diagnostics.s5941 urecpe v0.16b, v31.16b
5942 urecpe v2.8h, v4.8h
5943 urecpe v1.8b, v9.8b
5944 urecpe v13.4h, v21.4h
5945 urecpe v1.2d, v9.2d
6183 // CHECK-ERROR: urecpe v0.16b, v31.16b
6186 // CHECK-ERROR: urecpe v2.8h, v4.8h
6189 // CHECK-ERROR: urecpe v1.8b, v9.8b
6192 // CHECK-ERROR: urecpe v13.4h, v21.4h
6195 // CHECK-ERROR: urecpe v
[all...]
H A Darm64-advsimd.s604 urecpe.2s v0, v0
654 ; CHECK: urecpe.2s v0, v0 ; encoding: [0x00,0xc8,0xa1,0x0e]
/external/capstone/suite/MC/AArch64/
H A Dneon-simd-misc.s.cs195 0x06,0xc9,0xa1,0x4e = urecpe v6.4s, v8.4s
196 0x04,0xc8,0xa1,0x0e = urecpe v4.2s, v0.2s
/external/vixl/src/aarch64/
H A Dassembler-aarch64.h2003 void urecpe(const VRegister& vd, const VRegister& vn);
H A Dmacro-assembler-aarch64.h2363 V(urecpe, Urecpe) \
H A Dsimulator-aarch64.h2948 LogicVRegister urecpe(VectorFormat vform,
H A Dsimulator-aarch64.cc3189 urecpe(fpf, rd, rn);
H A Dassembler-aarch64.cc3404 void Assembler::urecpe(const VRegister& vd, const VRegister& vn) {
H A Dlogic-aarch64.cc4857 LogicVRegister Simulator::urecpe(VectorFormat vform, function in class:vixl::aarch64::Simulator
/external/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc2383 __ urecpe(v23.V2S(), v15.V2S());
2384 __ urecpe(v27.V4S(), v7.V4S());
H A Dtest-simulator-aarch64.cc4330 DEFINE_TEST_NEON_2SAME_2S_4S(urecpe, Basic)
/external/valgrind/none/tests/arm64/
H A Dfp_and_simd.stdout.exp[all...]

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