Searched refs:ushl (Results 1 - 17 of 17) sorted by relevance

/external/llvm/test/MC/AArch64/
H A Dneon-scalar-shift.s13 ushl d17, d31, d8
15 // CHECK: ushl d17, d31, d8 // encoding: [0xf1,0x47,0xe8,0x7e]
H A Dneon-shift.s28 ushl v0.8b, v1.8b, v2.8b
29 ushl v0.16b, v1.16b, v2.16b
30 ushl v0.4h, v1.4h, v2.4h
31 ushl v0.8h, v1.8h, v2.8h
32 ushl v0.2s, v1.2s, v2.2s
33 ushl v0.4s, v1.4s, v2.4s
34 ushl v0.2d, v1.2d, v2.2d
36 // CHECK: ushl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x44,0x22,0x2e]
37 // CHECK: ushl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x44,0x22,0x6e]
38 // CHECK: ushl v
[all...]
H A Dneon-diagnostics.s916 ushl v1.16b, v25.16b, v6.8h
922 // CHECK-ERROR: ushl v1.16b, v25.16b, v6.8h
972 ushl b2, b0, b1
978 // CHECK-ERROR: ushl b2, b0, b1
H A Darm64-advsimd.s370 ushl.8b v0, v0, v0
441 ; CHECK: ushl.8b v0, v0, v0 ; encoding: [0x00,0x44,0x20,0x2e]
/external/capstone/suite/MC/AArch64/
H A Dneon-scalar-shift.s.cs3 0xf1,0x47,0xe8,0x7e = ushl d17, d31, d8
H A Dneon-shift.s.cs9 0x20,0x44,0x22,0x2e = ushl v0.8b, v1.8b, v2.8b
10 0x20,0x44,0x22,0x6e = ushl v0.16b, v1.16b, v2.16b
11 0x20,0x44,0x62,0x2e = ushl v0.4h, v1.4h, v2.4h
12 0x20,0x44,0x62,0x6e = ushl v0.8h, v1.8h, v2.8h
13 0x20,0x44,0xa2,0x2e = ushl v0.2s, v1.2s, v2.2s
14 0x20,0x44,0xa2,0x6e = ushl v0.4s, v1.4s, v2.4s
15 0x20,0x44,0xe2,0x6e = ushl v0.2d, v1.2d, v2.2d
/external/libavc/common/armv8/
H A Dih264_resi_trans_quant_av8.s543 ushl v14.4s, v14.4s, v22.4s
544 ushl v15.4s, v15.4s, v22.4s
545 ushl v16.4s, v16.4s, v22.4s
546 ushl v17.4s, v17.4s, v22.4s
655 ushl v2.4s, v25.4s, v24.4s //>>qbit
656 ushl v3.4s, v26.4s, v24.4s //>>qbit
/external/libjpeg-turbo/simd/
H A Djsimd_arm64_neon.S2735 ushl v4.8h, v4.8h, v24.8h /* shift */
2736 ushl v5.8h, v5.8h, v25.8h
2737 ushl v6.8h, v6.8h, v26.8h
2738 ushl v7.8h, v7.8h, v27.8h
3338 ushl v24.8h, v24.8h, v0.8h
3339 ushl v25.8h, v25.8h, v1.8h
3340 ushl v26.8h, v26.8h, v2.8h
3341 ushl v27.8h, v27.8h, v3.8h
3342 ushl v28.8h, v28.8h, v4.8h
3343 ushl v2
[all...]
/external/vixl/src/aarch64/
H A Dsimulator-aarch64.cc3434 ushl(vf, rd, rn, rm);
3467 ushl(vf, rd, rn, rm).UnsignedSaturate(vf);
3473 ushl(vf, rd, rn, rm).Round(vf);
3479 ushl(vf, rd, rn, rm).Round(vf).UnsignedSaturate(vf);
4668 ushl(vf, rd, rn, rm);
4692 ushl(vf, rd, rn, rm).UnsignedSaturate(vf);
4698 ushl(vf, rd, rn, rm).Round(vf);
4704 ushl(vf, rd, rn, rm).Round(vf).UnsignedSaturate(vf);
H A Dlogic-aarch64.cc1645 return ushl(vform, dst, src, shiftreg);
1697 return ushl(vform, dst, extendedreg, shiftreg);
1709 return ushl(vform, dst, extendedreg, shiftreg);
1748 return ushl(vform, dst, src, shiftreg).UnsignedSaturate(vform);
1796 return ushl(vform, dst, src, shiftreg);
1970 LogicVRegister Simulator::ushl(VectorFormat vform, function in class:vixl::aarch64::Simulator
H A Dassembler-aarch64.h1742 void ushl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
H A Dmacro-assembler-aarch64.h2277 V(ushl, Ushl) \
H A Dsimulator-aarch64.h2292 LogicVRegister ushl(VectorFormat vform,
H A Dassembler-aarch64.cc2661 V(ushl, NEON_USHL, vd.IsVector() || vd.Is1D()) \
/external/vixl/test/aarch64/
H A Dtest-trace-aarch64.cc2417 __ ushl(d31, d0, d16);
2418 __ ushl(v0.V16B(), v6.V16B(), v2.V16B());
2419 __ ushl(v18.V2D(), v1.V2D(), v18.V2D());
2420 __ ushl(v27.V2S(), v7.V2S(), v29.V2S());
2421 __ ushl(v14.V4H(), v14.V4H(), v13.V4H());
2422 __ ushl(v22.V4S(), v4.V4S(), v9.V4S());
2423 __ ushl(v23.V8B(), v22.V8B(), v27.V8B());
2424 __ ushl(v21.V8H(), v25.V8H(), v8.V8H());
H A Dtest-simulator-aarch64.cc4120 DEFINE_TEST_NEON_3SAME(ushl, Basic)
4173 DEFINE_TEST_NEON_3SAME_SCALAR_D(ushl, Basic)
/external/valgrind/none/tests/arm64/
H A Dfp_and_simd.stdout.exp[all...]

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