Searched refs:vceq (Results 1 - 25 of 25) sorted by relevance

/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dneon-cmp-encoding.s3 vceq.i8 d16, d16, d17
4 vceq.i16 d16, d16, d17
5 vceq.i32 d16, d16, d17
6 vceq.f32 d16, d16, d17
7 vceq.i8 q8, q8, q9
8 vceq.i16 q8, q8, q9
9 vceq.i32 q8, q8, q9
10 vceq.f32 q8, q8, q9
12 @ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3]
13 @ CHECK: vceq
[all...]
/external/arm-neon-tests/
H A Dref_vceq.c26 #define INSN_NAME vceq
29 /* Extra tests for _p8 variants, which exist only for vceq */
H A DAndroid.mk25 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
H A DMakefile40 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
/external/capstone/suite/MC/ARM/
H A Dneon-cmp-encoding.s.cs2 0xb1,0x08,0x40,0xf3 = vceq.i8 d16, d16, d17
3 0xb1,0x08,0x50,0xf3 = vceq.i16 d16, d16, d17
4 0xb1,0x08,0x60,0xf3 = vceq.i32 d16, d16, d17
5 0xa1,0x0e,0x40,0xf2 = vceq.f32 d16, d16, d17
6 0xf2,0x08,0x40,0xf3 = vceq.i8 q8, q8, q9
7 0xf2,0x08,0x50,0xf3 = vceq.i16 q8, q8, q9
8 0xf2,0x08,0x60,0xf3 = vceq.i32 q8, q8, q9
9 0xe2,0x0e,0x40,0xf2 = vceq.f32 q8, q8, q9
48 0x20,0x01,0xf1,0xf3 = vceq.i8 d16, d16, #0
H A Dneon-bitwise-encoding.s.cs109 0x56,0xa8,0x1a,0xf3 = vceq.i16 q5, q5, q3
110 0x13,0x58,0x15,0xf3 = vceq.i16 d5, d5, d3
119 0x4a,0xa1,0xb5,0xf3 = vceq.i16 q5, q5, #0
120 0x05,0x51,0xb5,0xf3 = vceq.i16 d5, d5, #0
/external/llvm/test/MC/ARM/
H A Dneon-cmp-encoding.s3 vceq.i8 d16, d16, d17
4 vceq.i16 d16, d16, d17
5 vceq.i32 d16, d16, d17
6 vceq.f32 d16, d16, d17
7 vceq.i8 q8, q8, q9
8 vceq.i16 q8, q8, q9
9 vceq.i32 q8, q8, q9
10 vceq.f32 q8, q8, q9
12 @ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3]
13 @ CHECK: vceq
[all...]
H A Dfullfp16-neon-neg.s56 vceq.f16 d2, d3, d4
57 vceq.f16 q2, q3, q4
61 vceq.f16 d2, d3, #0
62 vceq.f16 q2, q3, #0
H A Dfullfp16-neon.s74 vceq.f16 d2, d3, d4
75 vceq.f16 q2, q3, q4
76 @ ARM: vceq.f16 d2, d3, d4 @ encoding: [0x04,0x2e,0x13,0xf2]
77 @ ARM: vceq.f16 q2, q3, q4 @ encoding: [0x48,0x4e,0x16,0xf2]
78 @ THUMB: vceq.f16 d2, d3, d4 @ encoding: [0x13,0xef,0x04,0x2e]
79 @ THUMB: vceq.f16 q2, q3, q4 @ encoding: [0x16,0xef,0x48,0x4e]
81 vceq.f16 d2, d3, #0
82 vceq.f16 q2, q3, #0
83 @ ARM: vceq.f16 d2, d3, #0 @ encoding: [0x03,0x25,0xb5,0xf3]
84 @ ARM: vceq
[all...]
H A Dneon-bitwise-encoding.s307 vceq.s16 q5, q3
308 vceq.s16 d5, d3
322 vceq.s16 q5, #0
323 vceq.s16 d5, #0
360 @ CHECK: vceq.i16 q5, q5, q3 @ encoding: [0x56,0xa8,0x1a,0xf3]
361 @ CHECK: vceq.i16 d5, d5, d3 @ encoding: [0x13,0x58,0x15,0xf3]
375 @ CHECK: vceq.i16 q5, q5, #0 @ encoding: [0x4a,0xa1,0xb5,0xf3]
376 @ CHECK: vceq.i16 d5, d5, #0 @ encoding: [0x05,0x51,0xb5,0xf3]
/external/libavc/common/arm/
H A Dih264_resi_trans_quant_a9.s215 vceq.s16 q5, q15, #0 @I compare with zero row 1 and 2 blk 1
216 vceq.s16 q6, q0 , #0 @I compare with zero row 1 and 2 blk 1
410 vceq.s16 q5, q15, #0 @I compare with zero row 1 and 2 blk 1
411 vceq.s16 q6, q0 , #0 @I compare with zero row 1 and 2 blk 1
557 vceq.s16 q5, q11, #0
558 vceq.s16 q6, q12, #0
673 vceq.s16 q7, q4, #0 @Compute nnz
/external/valgrind/none/tests/arm/
H A Dneon64.stdout.exp1603 vceq.i32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078
1604 vceq.i32 d0, d1, d2 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078
1605 vceq.i32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x00000078
1606 vceq.i32 d3, d4, d5 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x00000078
1607 vceq.i16 d6, d7, d8 :: Qd 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078
1608 vceq.i16 d6, d7, d8 :: Qd 0x00000000 0x00000000 Qm (i32)0x00000078 Qn (i32)0x00000078
1609 vceq.i8 d9, d10, d12 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x0000008c Qn (i32)0x00000078
1610 vceq.i8 d9, d10, d12 :: Qd 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x00000078
1611 vceq.i8 d0, d1, d2 :: Qd 0xffffff00 0xffffff00 Qm (i32)0x80000001 Qn (i32)0x80000002
1612 vceq
[all...]
H A Dneon128.stdout.exp1357 vceq.i32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x00000018 Qn (i32)0x00000078
1358 vceq.i32 q3, q4, q5 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x0000008c Qn (i32)0x00000078
1359 vceq.i16 q6, q7, q8 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00000078 Qn (i32)0x00000078
1360 vceq.i8 q9, q10, q12 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x0000008c Qn (i32)0x00000078
1361 vceq.i8 q0, q1, q2 :: Qd 0xffffff00 0xffffff00 0xffffff00 0xffffff00 Qm (i32)0x80000001 Qn (i32)0x80000002
1362 vceq.i16 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x00004001 Qn (i32)0x00004001
1363 vceq.i32 q0, q1, q2 :: Qd 0x00000000 0x00000000 0x00000000 0x00000000 Qm (i32)0x80000001 Qn (i32)0x80000002
1364 vceq.i8 q0, q1, q2 :: Qd 0x00ffff00 0x00ffff00 0x00ffff00 0x00ffff00 Qm (i32)0x80000001 Qn (i32)0x00000002
1365 vceq.i16 q0, q1, q2 :: Qd 0xffff0000 0xffff0000 0xffff0000 0xffff0000 Qm (i32)0x00000001 Qn (i32)0x00004001
1366 vceq
[all...]
/external/vixl/test/aarch32/
H A Dtest-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-a32.cc52 M(vceq) \
210 #include "aarch32/traces/assembler-cond-dt-drt-drd-drn-drm-float-f32-only-vceq-a32.h"
H A Dtest-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-t32.cc52 M(vceq) \
210 #include "aarch32/traces/assembler-cond-dt-drt-drd-drn-drm-float-f32-only-vceq-t32.h"
/external/v8/src/compiler/arm/
H A Dcode-generator-arm.cc1548 __ vceq(i.OutputSimd128Register(), i.InputSimd128Register(0),
1554 __ vceq(dst, i.InputSimd128Register(0), i.InputSimd128Register(1));
1620 __ vceq(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0),
1626 __ vceq(Neon32, dst, i.InputSimd128Register(0),
1732 __ vceq(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),
1738 __ vceq(Neon16, dst, i.InputSimd128Register(0),
1854 __ vceq(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0),
1860 __ vceq(Neon8, dst, i.InputSimd128Register(0), i.InputSimd128Register(1));
/external/libjpeg-turbo/simd/
H A Djsimd_arm_neon.S2745 vceq.i16 q0, q0, q8
2746 vceq.i16 q1, q1, q8
2747 vceq.i16 q2, q2, q8
2748 vceq.i16 q3, q3, q8
2749 vceq.i16 q4, q4, q8
2750 vceq.i16 q5, q5, q8
2751 vceq.i16 q6, q6, q8
2752 vceq.i16 q7, q7, q8
/external/vixl/src/aarch32/
H A Dassembler-aarch32.h3991 void vceq(Condition cond,
3996 void vceq(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { function in class:vixl::aarch32::Assembler
3997 vceq(al, dt, rd, rm, operand);
4000 void vceq(Condition cond,
4005 void vceq(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { function in class:vixl::aarch32::Assembler
4006 vceq(al, dt, rd, rm, operand);
4009 void vceq(
4011 void vceq(DataType dt, DRegister rd, DRegister rn, DRegister rm) { function in class:vixl::aarch32::Assembler
4012 vceq(al, dt, rd, rn, rm);
4015 void vceq(
4017 void vceq(DataType dt, QRegister rd, QRegister rn, QRegister rm) { function in class:vixl::aarch32::Assembler
[all...]
H A Ddisasm-aarch32.h1555 void vceq(Condition cond,
1561 void vceq(Condition cond,
1567 void vceq(
1570 void vceq(
H A Ddisasm-aarch32.cc4058 void Disassembler::vceq(Condition cond, function in class:vixl::aarch32::Disassembler
4072 void Disassembler::vceq(Condition cond, function in class:vixl::aarch32::Disassembler
4086 void Disassembler::vceq( function in class:vixl::aarch32::Disassembler
4097 void Disassembler::vceq( function in class:vixl::aarch32::Disassembler
[all...]
H A Dassembler-aarch32.cc14980 void Assembler::vceq(Condition cond, function in class:vixl::aarch32::Assembler
15017 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rm, operand);
15020 void Assembler::vceq(Condition cond, function in class:vixl::aarch32::Assembler
15057 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rm, operand);
15060 void Assembler::vceq( function in class:vixl::aarch32::Assembler
15103 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm);
15106 void Assembler::vceq( function in class:vixl::aarch32::Assembler
15149 Delegate(kVceq, &Assembler::vceq, cond, dt, rd, rn, rm);
H A Dmacro-assembler-aarch32.h5827 vceq(cond, dt, rd, rm, operand);
5845 vceq(cond, dt, rd, rm, operand);
5860 vceq(cond, dt, rd, rn, rm);
5875 vceq(cond, dt, rd, rn, rm);
/external/v8/src/arm/
H A Dassembler-arm.h1397 void vceq(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
1398 void vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
H A Dassembler-arm.cc4540 void Assembler::vceq(QwNeonRegister dst, QwNeonRegister src1, function in class:v8::internal::Assembler
4543 // Qd = vceq(Qn, Qm) SIMD floating point compare equal.
4548 void Assembler::vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, function in class:v8::internal::Assembler
4551 // Qd = vceq(Qn, Qm) SIMD integer compare equal.
/external/v8/src/s390/
H A Dconstants-s390.h545 V(vceq, VCEQ, 0xE7F8) /* type = VRR_B VECTOR COMPARE EQUAL */ \

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